JPS6397913U - - Google Patents
Info
- Publication number
- JPS6397913U JPS6397913U JP14186887U JP14186887U JPS6397913U JP S6397913 U JPS6397913 U JP S6397913U JP 14186887 U JP14186887 U JP 14186887U JP 14186887 U JP14186887 U JP 14186887U JP S6397913 U JPS6397913 U JP S6397913U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- collector
- base
- grounded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Description
第１図は従来のＩ２Ｌゲート回路の例を示し、
第２図ａおよびｂはそのデバイス構造の平面図お
よび断面図である。第３図および第４図は、本考
案の実施例を示す回路結線図であり、第５図は第
３図に対応するデバイス構造の平面図である。第
６図および第７図は本考案回路の応用を説明する
回路図、ブロツク図である。
１〜４……トランジスタ、５，６……抵抗。
FIG. 1 shows an example of a conventional I 2 L gate circuit,
Figures 2a and 2b are plan and cross-sectional views of the device structure. 3 and 4 are circuit connection diagrams showing an embodiment of the present invention, and FIG. 5 is a plan view of a device structure corresponding to FIG. 3. 6 and 7 are circuit diagrams and block diagrams illustrating the application of the circuit of the present invention. 1 to 4...transistor, 5,6...resistance.
Claims (1)
導電型の第２および第４のトランジスタと定電流
供給手段とを有し、前記第２のトランジスタのエ
ミツタを接地し、前記第２のトランジスタのコレ
クタに前記第１のトランジスタのエミツタを、前
記第２のトランジスタのベースに前記第１のトラ
ンジスタのコレクタを接続し、前記第１のトラン
ジスタのベースを接地し、前記第１のトランジス
タのエミツタと前記第２のトランジスタのコレク
タとの接地点に前記第３のトランジスタのエミツ
タを接続し、前記第３のトランジスタのベースを
接地し、前記第３のトランジスタのコレクタを前
記第４のトランジスタのベースに接続し、前記第
４のトランジスタのエミツタを接地し、かつ、前
記第１のトランジスタのエミツタと前記第３のト
ランジスタのエミツタと前記第２のトランジスタ
のコレクタとの接続点に前記定電流供給手段を接
続し、前記第２のトランジスタのベース又は前記
第４のトランジスタのベースに入力端子を接続し
、前記第４のトランジスタのコレクタに出力端子
を接続したことを特徴とする集積回路。 It has first and third transistors of one conductivity type, second and fourth transistors of opposite conductivity type, and constant current supply means, the emitter of the second transistor is grounded, and the emitter of the second transistor is grounded. The emitter of the first transistor is connected to the collector, the collector of the first transistor is connected to the base of the second transistor, the base of the first transistor is grounded, and the emitter of the first transistor and the The emitter of the third transistor is connected to a ground point with the collector of the second transistor, the base of the third transistor is grounded, and the collector of the third transistor is connected to the base of the fourth transistor. and the emitter of the fourth transistor is grounded, and the constant current supply means is connected to a connection point between the emitter of the first transistor, the emitter of the third transistor, and the collector of the second transistor. An integrated circuit characterized in that an input terminal is connected to the base of the second transistor or the base of the fourth transistor, and an output terminal is connected to the collector of the fourth transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14186887U JPS6397913U (en) | 1987-09-17 | 1987-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14186887U JPS6397913U (en) | 1987-09-17 | 1987-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6397913U true JPS6397913U (en) | 1988-06-24 |
Family
ID=31050060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14186887U Pending JPS6397913U (en) | 1987-09-17 | 1987-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6397913U (en) |
-
1987
- 1987-09-17 JP JP14186887U patent/JPS6397913U/ja active Pending