JPS5896391U - matrix circuit - Google Patents
matrix circuitInfo
- Publication number
- JPS5896391U JPS5896391U JP19127281U JP19127281U JPS5896391U JP S5896391 U JPS5896391 U JP S5896391U JP 19127281 U JP19127281 U JP 19127281U JP 19127281 U JP19127281 U JP 19127281U JP S5896391 U JPS5896391 U JP S5896391U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- collector load
- input
- side signal
- stereo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のマトリクス回路図、第２図は本考案実施
例の回路図で、第３図および第４図は本考案実施例の、
それぞれ（Ｌ＋Ｒ）信号の出力されること、および（Ｌ
−Ｒ）信号の出力されることを説明する等価回路図であ
る。第５図は本考案の変型実施例の回路図である。Fig. 1 is a conventional matrix circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Figs. 3 and 4 are circuit diagrams of an embodiment of the present invention.
(L+R) signals are output, and (L
-R) is an equivalent circuit diagram explaining that a signal is output. FIG. 5 is a circuit diagram of a modified embodiment of the present invention.
Claims (1)
不平衡差動増幅回路の、コレクタ負荷抵抗が大きい方の
トランジスタのベースにステレオ信号の右側信号を入力
し、コレクタ負荷抵抗が小さい方のトランジスタのベー
スに同ステレオ信号の左側隼号を入力し、上記のコレク
タ負荷抵抗が大きい方のトランジスタのコレクターより
、上記ステレオ信号の左側信号と右側信号の差信号を出
力し、上記両トランジスターのエミッタ側共通抵抗の非
接地側より上記ステレオ信号の左側信号と゛右側信号の
和信号を出力するよう構成された回路において、上記エ
ミッタ側共通抵抗をそれに代る抵抗要素として定電流回
路で置換したマトリクス回路。In an unbalanced differential amplifier circuit using two transistors with different collector load resistances, the right side signal of the stereo signal is input to the base of the transistor with larger collector load resistance, and the right side signal of the stereo signal is input to the base of the transistor with smaller collector load resistance. Input the left side signal of the same stereo signal into , output the difference signal between the left side signal and the right side signal of the above stereo signal from the collector of the transistor whose collector load resistance is larger, and connect the emitter side common resistance of both transistors. A matrix circuit configured to output a sum signal of the left side signal and the right side signal of the stereo signal from the non-grounded side of the circuit, wherein the emitter side common resistor is replaced with a constant current circuit as a resistive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19127281U JPS5896391U (en) | 1981-12-21 | 1981-12-21 | matrix circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19127281U JPS5896391U (en) | 1981-12-21 | 1981-12-21 | matrix circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5896391U true JPS5896391U (en) | 1983-06-30 |
Family
ID=30104744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19127281U Pending JPS5896391U (en) | 1981-12-21 | 1981-12-21 | matrix circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5896391U (en) |
-
1981
- 1981-12-21 JP JP19127281U patent/JPS5896391U/en active Pending
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