JPS5896322U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5896322U
JPS5896322U JP19088881U JP19088881U JPS5896322U JP S5896322 U JPS5896322 U JP S5896322U JP 19088881 U JP19088881 U JP 19088881U JP 19088881 U JP19088881 U JP 19088881U JP S5896322 U JPS5896322 U JP S5896322U
Authority
JP
Japan
Prior art keywords
potential
differential amplifier
muting
base
muting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19088881U
Other languages
Japanese (ja)
Other versions
JPH0122256Y2 (en
Inventor
芳郎 功力
渡辺　良彦
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP19088881U priority Critical patent/JPS5896322U/en
Publication of JPS5896322U publication Critical patent/JPS5896322U/en
Application granted granted Critical
Publication of JPH0122256Y2 publication Critical patent/JPH0122256Y2/ja
Granted legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のミューティング回路を示す回路−図、及
び第２図／！ま本考案によるミューティング回路の一実
施例を示す回路図である。 Ｑ□〜Ｑ、・・・トランジスタ、Ｄ３．Ｄ、・・・ダイ
オード。Figure 1 is a circuit diagram showing a conventional muting circuit, and Figure 2/! FIG. 1 is a circuit diagram showing an embodiment of a muting circuit according to the present invention. Q□~Q,...transistor, D3. D...Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] □　差動増幅器を構成する一対のトランジスタのそれぞ
れと並列に同一導電形のトランジスタをそれぞれ接続す
ると共にそれらのベースを相互接続・してなり、前記差
動増幅器の信号入力となるトランジスタのベースの電位
と前記相互接続したベースの電位との間の電位差を切換
えてミューティング動作を行なわせるようにしたミュー
ティング回路において、前記差動増幅器の信号入力にク
ランパーを設け、かつミューティング動作時における前
記電位差を前記クランパーのクランプ電圧よりも大きく
するようにしたことを特徴とするミューティング回路。□ Transistors of the same conductivity type are connected in parallel with each of a pair of transistors constituting a differential amplifier, and their bases are interconnected, and the potential of the base of the transistor that becomes the signal input of the differential amplifier is In the muting circuit, the muting operation is performed by switching the potential difference between the potential of the base and the potential of the interconnected base, and a clamper is provided at the signal input of the differential amplifier, and the potential difference during the muting operation is switched. A muting circuit characterized in that the voltage is set to be higher than the clamp voltage of the clamper.
JP19088881U 1981-12-23 1981-12-23 Muting circuit Granted JPS5896322U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19088881U JPS5896322U (en) 1981-12-23 1981-12-23 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19088881U JPS5896322U (en) 1981-12-23 1981-12-23 Muting circuit

Publications (2)

Publication Number Publication Date
JPS5896322U true JPS5896322U (en) 1983-06-30
JPH0122256Y2 JPH0122256Y2 (en) 1989-06-30

Family

ID=30104379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19088881U Granted JPS5896322U (en) 1981-12-23 1981-12-23 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5896322U (en)

Also Published As

Publication number Publication date
JPH0122256Y2 (en) 1989-06-30

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