JPS5861531U - limiter - Google Patents
limiterInfo
- Publication number
- JPS5861531U JPS5861531U JP15661181U JP15661181U JPS5861531U JP S5861531 U JPS5861531 U JP S5861531U JP 15661181 U JP15661181 U JP 15661181U JP 15661181 U JP15661181 U JP 15661181U JP S5861531 U JPS5861531 U JP S5861531U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- reference voltage
- supplied
- collectors
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のりミツターの接続図、第2図及び第3図
はその動作説明図、第4図はこの考案に係るリミッタ−
の−例を示す接続図、第5図はそ −の動作説明
に供する上記リミッタ−の要部の接続図である。
Q1〜Q4は第1〜第4のトランジスタ、1は入力端子
、2は出力端子、VDは基準電圧、Sは入力信号、So
は出力信号である。Figure 1 is a connection diagram of a conventional limiter, Figures 2 and 3 are illustrations of its operation, and Figure 4 is a limiter according to this invention.
FIG. 5 is a connection diagram of the main parts of the limiter to explain its operation. Q1 to Q4 are first to fourth transistors, 1 is an input terminal, 2 is an output terminal, VD is a reference voltage, S is an input signal, So
is the output signal.
Claims (1)
れらトランジスタのコレクタに夫々接続された抵抗と、
これら第1及び第2のトランジスタのコレクタにベース
が、エミッタにコレクタが接続された上記第1及び第2
のトランジスタと異る導電型の第3及び第4のトランジ
スタとで構成され、上記第2のトランジスタに基準電圧
が供給され、上記第1のトランジスタに入力信号が供給
され、上記第1及び第2のトランジスタの共通エミッタ
より、上記基準電圧レベル以上の入力信号が上記基準電
圧レベルに制限された出力信号が得 、られるように
なされたりミツター。emitter-coupled first and second transistors, and resistors connected to the collectors of these transistors, respectively;
The first and second transistors have bases connected to collectors and collectors connected to emitters of the first and second transistors.
and third and fourth transistors of different conductivity types, the second transistor is supplied with a reference voltage, the first transistor is supplied with an input signal, and the first and second transistors are supplied with a reference voltage. The common emitters of the transistors are configured such that an input signal above the reference voltage level results in an output signal limited to the reference voltage level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15661181U JPS5861531U (en) | 1981-10-21 | 1981-10-21 | limiter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15661181U JPS5861531U (en) | 1981-10-21 | 1981-10-21 | limiter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5861531U true JPS5861531U (en) | 1983-04-25 |
Family
ID=29949146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15661181U Pending JPS5861531U (en) | 1981-10-21 | 1981-10-21 | limiter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5861531U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165013A (en) * | 1979-06-09 | 1980-12-23 | Matsushita Electric Ind Co Ltd | Clip circuit |
-
1981
- 1981-10-21 JP JP15661181U patent/JPS5861531U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165013A (en) * | 1979-06-09 | 1980-12-23 | Matsushita Electric Ind Co Ltd | Clip circuit |
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