JPS58132413U - push-pull amplifier circuit - Google Patents

push-pull amplifier circuit

Info

Publication number
JPS58132413U
JPS58132413U JP2924182U JP2924182U JPS58132413U JP S58132413 U JPS58132413 U JP S58132413U JP 2924182 U JP2924182 U JP 2924182U JP 2924182 U JP2924182 U JP 2924182U JP S58132413 U JPS58132413 U JP S58132413U
Authority
JP
Japan
Prior art keywords
transistors
push
amplifier circuit
pull amplifier
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2924182U
Other languages
Japanese (ja)
Inventor
藤原 柾実
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP2924182U priority Critical patent/JPS58132413U/en
Publication of JPS58132413U publication Critical patent/JPS58132413U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す回路図、第2図、第3図、第4図
はそれぞれ本考案の一実施例を示す回路図である。 図中、3及び4はFET、IQ及び11はバイポーラト
ランジスタ、14及び17は可変抵抗器、15.16及
び18は抵抗器である。
FIG. 1 is a circuit diagram showing a conventional example, and FIGS. 2, 3, and 4 are circuit diagrams each showing an embodiment of the present invention. In the figure, 3 and 4 are FETs, IQ and 11 are bipolar transistors, 14 and 17 are variable resistors, and 15, 16 and 18 are resistors.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 導電型の異なる1対のトランジスタに入力信号を印加し
、上記1対のトランジスタのドレイン又はコレクタより
出力信号を得るプッシュプル増幅回路において、前記1
対のトランジスタのドレイン又はコレクタをそれぞれ抵
抗を介して接地すると共に、前記1対のトランジスタの
ドレイン又はコレクタを、少くとも一方の抵抗値が可変
になされた抵抗を介してそれぞれ出力端子に接続したこ
とを特徴とするプッシュプル増幅回路。
In the push-pull amplifier circuit, an input signal is applied to a pair of transistors having different conductivity types, and an output signal is obtained from the drain or collector of the pair of transistors.
The drains or collectors of the pair of transistors are each grounded via a resistor, and the drains or collectors of the pair of transistors are each connected to an output terminal via a resistor in which at least one of the transistors has a variable resistance value. A push-pull amplifier circuit featuring
JP2924182U 1982-03-02 1982-03-02 push-pull amplifier circuit Pending JPS58132413U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2924182U JPS58132413U (en) 1982-03-02 1982-03-02 push-pull amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2924182U JPS58132413U (en) 1982-03-02 1982-03-02 push-pull amplifier circuit

Publications (1)

Publication Number Publication Date
JPS58132413U true JPS58132413U (en) 1983-09-07

Family

ID=30041049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2924182U Pending JPS58132413U (en) 1982-03-02 1982-03-02 push-pull amplifier circuit

Country Status (1)

Country Link
JP (1) JPS58132413U (en)

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