JPS5893010U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS5893010U JPS5893010U JP18998681U JP18998681U JPS5893010U JP S5893010 U JPS5893010 U JP S5893010U JP 18998681 U JP18998681 U JP 18998681U JP 18998681 U JP18998681 U JP 18998681U JP S5893010 U JPS5893010 U JP S5893010U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- transistor
- muting circuit
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
- Noise Elimination (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案のミューティング回路における一実施例の概
略電気的結線図である。
1・・・・・・FM検波回路、2・・・・・・同調指示
用電圧発生回路、3・・・・・・出力増幅器、Ql・・
・・・・信号増幅用トランジスタ、Q2・・・・・・ミ
ューティング用トランジスタ、R1−R6・・・・・・
抵抗。The figure is a schematic electrical wiring diagram of one embodiment of the muting circuit of the present invention. 1...FM detection circuit, 2...Tuning instruction voltage generation circuit, 3...Output amplifier, Ql...
...Transistor for signal amplification, Q2...Transistor for muting, R1-R6...
resistance.
Claims (1)
ンジスタを接続し、このミューティング用トランジスタ
をオン1、オフ制御することにより上記増幅用トランジ
スタのゲインを制御すると共に上記ミューティング用ト
ランジスタに並列に抵抗を接続して成るミューティング
回路。A muting transistor is connected in series to the signal amplification transistor, and the gain of the amplification transistor is controlled by turning on and off the muting transistor, and a resistor is connected in parallel to the muting transistor. A muting circuit consisting of
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18998681U JPS5893010U (en) | 1981-12-18 | 1981-12-18 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18998681U JPS5893010U (en) | 1981-12-18 | 1981-12-18 | Muting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5893010U true JPS5893010U (en) | 1983-06-23 |
Family
ID=29994264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18998681U Pending JPS5893010U (en) | 1981-12-18 | 1981-12-18 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5893010U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220405A (en) * | 1985-07-18 | 1987-01-29 | Pioneer Electronic Corp | Amplification degree adjusting circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS495310B1 (en) * | 1969-02-27 | 1974-02-06 | ||
JPS4962104A (en) * | 1972-09-14 | 1974-06-17 |
-
1981
- 1981-12-18 JP JP18998681U patent/JPS5893010U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS495310B1 (en) * | 1969-02-27 | 1974-02-06 | ||
JPS4962104A (en) * | 1972-09-14 | 1974-06-17 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6220405A (en) * | 1985-07-18 | 1987-01-29 | Pioneer Electronic Corp | Amplification degree adjusting circuit |
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