JPS58105700U - Signal amplifier with calibration - Google Patents
Signal amplifier with calibrationInfo
- Publication number
- JPS58105700U JPS58105700U JP245782U JP245782U JPS58105700U JP S58105700 U JPS58105700 U JP S58105700U JP 245782 U JP245782 U JP 245782U JP 245782 U JP245782 U JP 245782U JP S58105700 U JPS58105700 U JP S58105700U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- calibration
- circuit
- amplifier
- signal amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
□ 第１図は本考案の実施例のブロック図、第２図は
前記の動作を説明するための波形図である。図において
、
１・・・・・・センサ、セ・・・・・・加算器、３・・
・・・・信号増幅器、４・・・・・・判定回路、５・・
・・・・ゲート回路、６・曲・基準信号発生回路、７・
・・・・・校正信号発生回路である。□ FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the above operation. In the figure, 1...sensor, 3...adder, 3...
... Signal amplifier, 4 ... Judgment circuit, 5 ...
...Gate circuit, 6. Song/reference signal generation circuit, 7.
...This is a calibration signal generation circuit.
Claims (1)
う校正つき信号増幅器において、前記重畳信号をその増
幅器の飽和レベル近（の所定電圧に対して比較するレベ
ル判定回路と、基準電圧を形成する基準電圧発生回路と
、前記レベル判定回路が前記重畳信号を前記所定電圧よ
り大きいと判定したとき前記基準電圧を出力するゲート
回路と、このゲート回路の出力を前記重畳信号に印加す
る加算回路とを含み、前記加算回路の出力を飽和し・な
いように増幅させたことを特徴とする校正付信号増幅器
。In a signal amplifier with calibration that superimposes a calibration signal on an input signal and amplifies the superimposed signal, a level determination circuit that compares the superimposed signal with a predetermined voltage (near the saturation level of the amplifier) and a reference voltage is formed. a reference voltage generation circuit that outputs the reference voltage when the level determination circuit determines that the superimposed signal is higher than the predetermined voltage; and an adder circuit that applies the output of the gate circuit to the superimposed signal. 1. A signal amplifier with calibration, characterized in that the output of the adder circuit is amplified so as not to be saturated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP245782U JPS58105700U (en) | 1982-01-12 | 1982-01-12 | Signal amplifier with calibration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP245782U JPS58105700U (en) | 1982-01-12 | 1982-01-12 | Signal amplifier with calibration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58105700U true JPS58105700U (en) | 1983-07-18 |
Family
ID=30015440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP245782U Pending JPS58105700U (en) | 1982-01-12 | 1982-01-12 | Signal amplifier with calibration |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58105700U (en) |
-
1982
- 1982-01-12 JP JP245782U patent/JPS58105700U/en active Pending
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