JPS615014U - Operation level optimization control circuit - Google Patents
Operation level optimization control circuitInfo
- Publication number
- JPS615014U JPS615014U JP8967784U JP8967784U JPS615014U JP S615014 U JPS615014 U JP S615014U JP 8967784 U JP8967784 U JP 8967784U JP 8967784 U JP8967784 U JP 8967784U JP S615014 U JPS615014 U JP S615014U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- operation level
- control circuit
- optimization control
- level optimization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第１図は、この考案の一実施例を示すブロック図である
。
第２図は、第１図の回路の実際の設計例を示す回路図で
ある。
１０・・・入力端子、１２・・・増幅器、１４・・・被
制御回路、１６・・・減衰器、１８・・・出力端子、２
０・・・レベル検出回路、２２・・・オーバロードイン
ジケータ。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of this invention. FIG. 2 is a circuit diagram showing an actual design example of the circuit shown in FIG. 10... Input terminal, 12... Amplifier, 14... Controlled circuit, 16... Attenuator, 18... Output terminal, 2
0... Level detection circuit, 22... Overload indicator.
Claims (1)
増幅回路と、被制御回路の出力信号を減衰して出力する
減衰回路と、被制御回路のオーバロード状態を検出する
回路と、前記増幅回路のゲインと前記減衰回路の減衰率
を略一定の相補的な関係を維持して連動して可変する手
段とを具えたことを特徴とする動作レベル最適化制御回
路。an amplifier circuit that amplifies an input signal of the controlled circuit and inputs it to the controlled circuit; an attenuation circuit that attenuates and outputs the output signal of the controlled circuit; and a circuit that detects an overload state of the controlled circuit; An operation level optimization control circuit characterized by comprising means for varying the gain of the amplifier circuit and the attenuation rate of the attenuation circuit in conjunction with each other while maintaining a substantially constant complementary relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8967784U JPS615014U (en) | 1984-06-15 | 1984-06-15 | Operation level optimization control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8967784U JPS615014U (en) | 1984-06-15 | 1984-06-15 | Operation level optimization control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615014U true JPS615014U (en) | 1986-01-13 |
Family
ID=30643977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8967784U Pending JPS615014U (en) | 1984-06-15 | 1984-06-15 | Operation level optimization control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615014U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01135674U (en) * | 1988-03-10 | 1989-09-18 |
-
1984
- 1984-06-15 JP JP8967784U patent/JPS615014U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01135674U (en) * | 1988-03-10 | 1989-09-18 | ||
| JPH0517823Y2 (en) * | 1988-03-10 | 1993-05-12 |
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