JPS58141609U - Amplifier - Google Patents

Amplifier

Info

Publication number
JPS58141609U
JPS58141609U JP3917282U JP3917282U JPS58141609U JP S58141609 U JPS58141609 U JP S58141609U JP 3917282 U JP3917282 U JP 3917282U JP 3917282 U JP3917282 U JP 3917282U JP S58141609 U JPS58141609 U JP S58141609U
Authority
JP
Japan
Prior art keywords
input signal
amplifier
delayed
detecting
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3917282U
Other languages
Japanese (ja)
Inventor
育亮 鷲見
Original Assignee
三洋電機株式会社
鳥取三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社, 鳥取三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP3917282U priority Critical patent/JPS58141609U/en
Publication of JPS58141609U publication Critical patent/JPS58141609U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の増幅装置の構成を示す図、第2図、第
3図は本考案の他の実施例の構成を示す図である。 2・・・・・・ディジタル遅延回路、3・・・・・・D
/A変換器、4・・・・・・電力増幅器、6・・・・・
・レベル検出回路、7・・・・・・電源回路、8・・・
・・・アナログ遅延回路、9・・・・・・A/D変換器
FIG. 1 is a diagram showing the configuration of an amplifying device of the present invention, and FIGS. 2 and 3 are diagrams showing the configuration of other embodiments of the present invention. 2...Digital delay circuit, 3...D
/A converter, 4... Power amplifier, 6...
・Level detection circuit, 7...Power supply circuit, 8...
...Analog delay circuit, 9...A/D converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電力増幅器に入力される入力信号を所定期間遅延させる
遅延手段と、遅延される前の入力信号レベルを検出する
レベル検出回路と、該回路の出力により制御され入力信
号レベルに対応した電源電圧を前記電力増幅器に供給す
る電源回路で構成したことを特徴とする増幅装置。
a delay means for delaying the input signal input to the power amplifier for a predetermined period; a level detection circuit for detecting the input signal level before being delayed; and a level detection circuit for detecting the input signal level before being delayed; An amplifier device characterized by comprising a power supply circuit that supplies a power amplifier.
JP3917282U 1982-03-18 1982-03-18 Amplifier Pending JPS58141609U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3917282U JPS58141609U (en) 1982-03-18 1982-03-18 Amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3917282U JPS58141609U (en) 1982-03-18 1982-03-18 Amplifier

Publications (1)

Publication Number Publication Date
JPS58141609U true JPS58141609U (en) 1983-09-24

Family

ID=30050474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3917282U Pending JPS58141609U (en) 1982-03-18 1982-03-18 Amplifier

Country Status (1)

Country Link
JP (1) JPS58141609U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572107A (en) * 1980-06-04 1982-01-07 Pioneer Electronic Corp Power supply circuit of electric power amplifier
JPS5715509A (en) * 1980-07-03 1982-01-26 Victor Co Of Japan Ltd Power supply circuit for power amplifier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572107A (en) * 1980-06-04 1982-01-07 Pioneer Electronic Corp Power supply circuit of electric power amplifier
JPS5715509A (en) * 1980-07-03 1982-01-26 Victor Co Of Japan Ltd Power supply circuit for power amplifier

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