JPS58123614U - amplifier circuit - Google Patents
amplifier circuitInfo
- Publication number
- JPS58123614U JPS58123614U JP1849582U JP1849582U JPS58123614U JP S58123614 U JPS58123614 U JP S58123614U JP 1849582 U JP1849582 U JP 1849582U JP 1849582 U JP1849582 U JP 1849582U JP S58123614 U JPS58123614 U JP S58123614U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- resistor
- input terminal
- differential amplifier
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来技術の出力増幅回路図、第２、第３図は本
考案の出力増幅回路図である。
１・・・・・・差動増幅器、２・・・・・・抵抗器、３
・・・・・・出力 一端子、４・・・・・・負
荷抵抗。FIG. 1 is a diagram of an output amplification circuit of the prior art, and FIGS. 2 and 3 are diagrams of an output amplification circuit of the present invention. 1...Differential amplifier, 2...Resistor, 3
...Output 1 terminal, 4...Load resistance.
Claims (1)
出力を抵抗器を介してその差動増幅器の入力端子の負入
力に接続し更に負入力端子と地気間に抵抗器を接続し、
かつ差動増幅器の出力端子から抵抗器を介して本増幅回
路の出力端とし、その出力端から抵抗器を介して前記差
動増幅器の正入力端子に接続し、その正入力端子に更に
抵抗器を接続してその抵抗器を介した点を増幅回路の入
力端として構成される事を特徴とする増幅回路。In an amplifier circuit using a differential amplifier, the output of the differential amplifier is connected to the negative input of the input terminal of the differential amplifier via a resistor, and a resistor is further connected between the negative input terminal and the ground,
The output terminal of the differential amplifier is connected to the output terminal of the present amplifier circuit via a resistor, the output terminal is connected to the positive input terminal of the differential amplifier via the resistor, and the positive input terminal is further connected to the output terminal of the amplifier circuit. An amplifier circuit characterized in that a point connected through a resistor is configured as an input terminal of the amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1849582U JPS58123614U (en) | 1982-02-15 | 1982-02-15 | amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1849582U JPS58123614U (en) | 1982-02-15 | 1982-02-15 | amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123614U true JPS58123614U (en) | 1983-08-23 |
Family
ID=30030747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1849582U Pending JPS58123614U (en) | 1982-02-15 | 1982-02-15 | amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123614U (en) |
-
1982
- 1982-02-15 JP JP1849582U patent/JPS58123614U/en active Pending
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