JPS6133520U - differential amplifier circuit - Google Patents
differential amplifier circuitInfo
- Publication number
- JPS6133520U JPS6133520U JP11450984U JP11450984U JPS6133520U JP S6133520 U JPS6133520 U JP S6133520U JP 11450984 U JP11450984 U JP 11450984U JP 11450984 U JP11450984 U JP 11450984U JP S6133520 U JPS6133520 U JP S6133520U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- positive
- pair
- negative input
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は、本考案に係る回路の接続図、第３
図は従来回路の接続図である。
１・・・正入力端子、２・・・負入力端子、３・・・出
力端子、４・・・基準電位端子、５・・・正電源端子、
６・・・負電源端子、７，８・・・定電流源、Ｑ１〜Ｑ
４・・・トランジスタ、Ｕ１・・・演算増幅器、Ｒ１〜
Ｒ６・・・抵抗。Figures 1 and 2 are connection diagrams of the circuit according to the present invention;
The figure is a connection diagram of a conventional circuit. 1...Positive input terminal, 2...Negative input terminal, 3...Output terminal, 4...Reference potential terminal, 5...Positive power supply terminal,
6... Negative power supply terminal, 7, 8... Constant current source, Q1~Q
4...Transistor, U1...Operation amplifier, R1~
R6...Resistance.
Claims (1)
信号を得る出力端子と、前記正、負入力端子にそれぞれ
ベースが接続されエミツタが抵抗と定電流源を介して負
電源端子に接続されコレクタがそれぞれ抵抗を介して正
電源端子に接続された一対のトランジスタＱｌ，Ｑ２と
、この一対のトランジスタの各コレクタに正負の入力端
が接続され出力端が前記出力端子に接続された演算増幅
器と、エミツタが抵抗と定電流源を介して負電源端子に
接続され各コレクタが前記トランジスタＱ１，Ｑ２のコ
レクタにそれぞれ接続された一対のトランジスタＱ３，
Ｑ４とを具備し、前記一対のトランジスタＱ３，Ｑ４の
うちの一方のトランジスタＱ３のベースを基準電位端子
に、他方のトランジスタＱ４のベースを前記演算増幅器
の出力端にそれぞれ接続した差動増幅回路。The positive and negative input terminals to which positive and negative input voltages are applied, the output terminal from which the output signal is obtained, and the bases are connected to the positive and negative input terminals, respectively, and the emitters are connected to the negative power supply terminal through a resistor and a constant current source. a pair of transistors Ql and Q2, each having its collector connected to the positive power supply terminal via a resistor, the positive and negative input terminals being connected to the respective collectors of this pair of transistors, and the output terminal thereof being connected to the output terminal. an operational amplifier, a pair of transistors Q3 whose emitters are connected to a negative power supply terminal via a resistor and a constant current source, and whose collectors are respectively connected to the collectors of the transistors Q1 and Q2;
Q4, the base of one transistor Q3 of the pair of transistors Q3 and Q4 is connected to a reference potential terminal, and the base of the other transistor Q4 is connected to the output terminal of the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11450984U JPS6133520U (en) | 1984-07-27 | 1984-07-27 | differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11450984U JPS6133520U (en) | 1984-07-27 | 1984-07-27 | differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6133520U true JPS6133520U (en) | 1986-02-28 |
| JPH0317455Y2 JPH0317455Y2 (en) | 1991-04-12 |
Family
ID=30673528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11450984U Granted JPS6133520U (en) | 1984-07-27 | 1984-07-27 | differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6133520U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04329009A (en) * | 1991-03-27 | 1992-11-17 | Internatl Business Mach Corp <Ibm> | All differential follower using operational amplifier |
| JP5759644B1 (en) * | 2015-01-30 | 2015-08-05 | ソニックス株式会社 | Differential amplifier circuit |
-
1984
- 1984-07-27 JP JP11450984U patent/JPS6133520U/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04329009A (en) * | 1991-03-27 | 1992-11-17 | Internatl Business Mach Corp <Ibm> | All differential follower using operational amplifier |
| JP5759644B1 (en) * | 2015-01-30 | 2015-08-05 | ソニックス株式会社 | Differential amplifier circuit |
| WO2016121943A1 (en) * | 2015-01-30 | 2016-08-04 | Ｓｉｍｐｌｅｘ Ｑｕａｎｔｕｍ株式会社 | Differential amplification circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0317455Y2 (en) | 1991-04-12 |
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