JPS6123714U - bias circuit - Google Patents
bias circuitInfo
- Publication number
- JPS6123714U JPS6123714U JP10728184U JP10728184U JPS6123714U JP S6123714 U JPS6123714 U JP S6123714U JP 10728184 U JP10728184 U JP 10728184U JP 10728184 U JP10728184 U JP 10728184U JP S6123714 U JPS6123714 U JP S6123714U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- resistor
- transistor
- bias circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は従来のバイアス回路、第３図は本
考案の一実施例の回路を示す。
１． ２） ３・・・・・・抵抗、４・・・・・・演算
増幅器、５・・・・・・トランジスタ、６・・・・・・
電源電圧、７・・・・・・定電圧ダイオード、８，９・
・・・・・抵抗。1 and 2 show a conventional bias circuit, and FIG. 3 shows a circuit according to an embodiment of the present invention. 1. 2) 3...Resistor, 4...Operation amplifier, 5...Transistor, 6...
Power supply voltage, 7... Constant voltage diode, 8, 9.
·····resistance.
Claims (1)
抗を介して電源に接続し、定電圧ダイオードのカソード
端子を前記電源に接続し、アノ一ド端子は第２の抵抗を
介して接地されており、さらに直列接続された第３およ
び第４の抵抗が前記定電圧ダイオードと並列に接続され
、該第３および第４の抵抗の接続点ならびに前記第１の
抵抗およびトランジスタの接続点のそれぞれが演算増幅
器の反転入力端子な４びに非反転入力端子に接続され、
該演算増幅器の出力端子が前記トランジスタのベース端
子に接続されていることを特徴とするバイアス回路。A collector terminal of a transistor whose emitter is grounded is connected to a power supply via a first resistor, a cathode terminal of a constant voltage diode is connected to the power supply, and an anode terminal is grounded via a second resistor, Further, third and fourth resistors connected in series are connected in parallel with the voltage regulator diode, and a connection point between the third and fourth resistors and a connection point between the first resistor and the transistor are each connected to an operational amplifier. is connected to the inverting input terminal 4 and the non-inverting input terminal of
A bias circuit characterized in that an output terminal of the operational amplifier is connected to a base terminal of the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10728184U JPS6123714U (en) | 1984-07-16 | 1984-07-16 | bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10728184U JPS6123714U (en) | 1984-07-16 | 1984-07-16 | bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123714U true JPS6123714U (en) | 1986-02-12 |
Family
ID=30666534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10728184U Pending JPS6123714U (en) | 1984-07-16 | 1984-07-16 | bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123714U (en) |
-
1984
- 1984-07-16 JP JP10728184U patent/JPS6123714U/en active Pending
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