JPS586417U - variable gain amplifier - Google Patents
variable gain amplifierInfo
- Publication number
- JPS586417U JPS586417U JP10016681U JP10016681U JPS586417U JP S586417 U JPS586417 U JP S586417U JP 10016681 U JP10016681 U JP 10016681U JP 10016681 U JP10016681 U JP 10016681U JP S586417 U JPS586417 U JP S586417U
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- transistors
- power supply
- variable gain
- gain amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の増幅器の回路図、第２図は本考案になる
可変利得増幅器の一実施例の回路図である。 。
図中、１，１′は入力端子、２．２′は出力端子、３は
第１の差動増幅器、４は第２の差動増幅器、５は制御端
子、Ｑｌ、 Ｑ２． Ｑｓ、 Ｏｅは差動トランジスタ
、Ｑ３は第１のトランジスタ、Ｑ４は第２のトランジス
タ、Ｑｌは制御トランジスタである。FIG. 1 is a circuit diagram of a conventional amplifier, and FIG. 2 is a circuit diagram of an embodiment of a variable gain amplifier according to the present invention. . In the figure, 1, 1' are input terminals, 2, 2' are output terminals, 3 is a first differential amplifier, 4 is a second differential amplifier, 5 is a control terminal, Ql, Q2. Qs and Oe are differential transistors, Q3 is a first transistor, Q4 is a second transistor, and Ql is a control transistor.
Claims (2)
構成され信号がベースに入力される第１の差動増幅器と
、前記第１の差動増幅器の各トランジスタのコレクタに
それぞれエミッタが接続され、共にコレクタが電源に接
続され、ベースが適当な電位点に接続された第１及び第
２のトランジスタと、前記第１の差動増幅器の両コレク
タが夫々ベースに接続され、少なくとも一方のコレクタ
が負荷抵抗を介してそれぞれ電源に接続され、エミッタ
が共通接続されて定電源に接続された２個のトランジス
タで構成された第２の差動増幅器と、前記第１の差動増
幅器の共通エミッタ電流を制御する電流制御手段を備え
たことを特徴とする可変利得増幅器。(1) a first differential amplifier composed of two transistors whose emitters are commonly connected, and a signal is input to the base; the emitter is connected to the collector of each transistor of the first differential amplifier; First and second transistors each have their collectors connected to a power supply and their bases connected to an appropriate potential point, and both collectors of the first differential amplifier are connected to their respective bases, and at least one collector is connected to a load. A second differential amplifier composed of two transistors each connected to a power supply via a resistor and whose emitters are connected in common and connected to a constant power supply, and a common emitter current of the first differential amplifier. A variable gain amplifier characterized by comprising current control means for controlling the current.
電源間に夫々電流源または抵抗を接続してなる実用新案
登録請求の範囲第１項記載の可変利得増幅器。(2) The variable gain amplifier according to claim 1, wherein a current source or a resistor is connected between the emitters of the first and second transistors and the power supply, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10016681U JPS586417U (en) | 1981-07-07 | 1981-07-07 | variable gain amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10016681U JPS586417U (en) | 1981-07-07 | 1981-07-07 | variable gain amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS586417U true JPS586417U (en) | 1983-01-17 |
Family
ID=29894871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10016681U Pending JPS586417U (en) | 1981-07-07 | 1981-07-07 | variable gain amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS586417U (en) |
-
1981
- 1981-07-07 JP JP10016681U patent/JPS586417U/en active Pending
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