JPS617137U - Control circuit for multivalued logic circuit - Google Patents
Control circuit for multivalued logic circuitInfo
- Publication number
- JPS617137U JPS617137U JP9171784U JP9171784U JPS617137U JP S617137 U JPS617137 U JP S617137U JP 9171784 U JP9171784 U JP 9171784U JP 9171784 U JP9171784 U JP 9171784U JP S617137 U JPS617137 U JP S617137U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- control circuit
- multivalued logic
- logic circuit
- differential amplifiers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の多値論理回路の制御回路の回路図、第
２図は同回路の各点の状態を示す状態図である。
主な図番の説明、ス・・・第１の差動増幅器、ル・・第
２の差動増幅器、直・・・第３の差動増幅器、１ス・・
・分圧回路、１７， １８， １９， ２０・・・
制御出力トランジスタ、２４，２５，２６，２７・・・
出力端子。FIG. 1 is a circuit diagram of a control circuit of a multivalued logic circuit of the present invention, and FIG. 2 is a state diagram showing the states of each point of the circuit. Explanation of main figure numbers, S...1st differential amplifier, L...2nd differential amplifier, direct...3rd differential amplifier, 1st...
・Voltage dividing circuit, 17, 18, 19, 20...
Control output transistors, 24, 25, 26, 27...
Output terminal.
Claims (1)
接続された複数の差動増幅器と、該差動増幅器の出力端
に設けた負荷と、前記各差動増幅器の一方のベースに各
接続点が接続された複数の抵抗より成る分圧回路と、前
記差動増幅器の他方のベースに接続された入力端子とを
備え、該入力端子に加えられる入力信号に応じて、前記
差動増幅器の１負荷より出力信号を択一的に導出するこ
とを特徴とした多値論理回路の制御回路。a plurality of differential amplifiers whose emitters are commonly connected and a constant current source is connected to each emitter; a load provided at the output end of the differential amplifier; and a connection point at one base of each of the differential amplifiers. and an input terminal connected to the other base of the differential amplifier, and one of the differential amplifiers is A control circuit for a multivalued logic circuit characterized by selectively deriving an output signal from a load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171784U JPS617137U (en) | 1984-06-19 | 1984-06-19 | Control circuit for multivalued logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171784U JPS617137U (en) | 1984-06-19 | 1984-06-19 | Control circuit for multivalued logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS617137U true JPS617137U (en) | 1986-01-17 |
Family
ID=30647855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9171784U Pending JPS617137U (en) | 1984-06-19 | 1984-06-19 | Control circuit for multivalued logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS617137U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01128520U (en) * | 1988-02-26 | 1989-09-01 | ||
| JPH01130928U (en) * | 1988-03-02 | 1989-09-06 |
-
1984
- 1984-06-19 JP JP9171784U patent/JPS617137U/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01128520U (en) * | 1988-02-26 | 1989-09-01 | ||
| JPH059311Y2 (en) * | 1988-02-26 | 1993-03-08 | ||
| JPH01130928U (en) * | 1988-03-02 | 1989-09-06 |
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