JPS5893013U - Output transistor current limit circuit - Google Patents

Output transistor current limit circuit

Info

Publication number
JPS5893013U
JPS5893013U JP18715681U JP18715681U JPS5893013U JP S5893013 U JPS5893013 U JP S5893013U JP 18715681 U JP18715681 U JP 18715681U JP 18715681 U JP18715681 U JP 18715681U JP S5893013 U JPS5893013 U JP S5893013U
Authority
JP
Japan
Prior art keywords
output transistor
differential amplifier
output
current limit
limit circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18715681U
Other languages
Japanese (ja)
Inventor
高木 次男
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP18715681U priority Critical patent/JPS5893013U/en
Publication of JPS5893013U publication Critical patent/JPS5893013U/en
Pending legal-status Critical Current

Links

Landscapes

  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例を示す回路図。図中、9及び10
はオペアンプ、5及び6はツェナーダイオード、21及
び22は出力トランジスタである。
The figure is a circuit diagram showing an embodiment of the present invention. In the figure, 9 and 10
is an operational amplifier, 5 and 6 are Zener diodes, and 21 and 22 are output transistors.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 出力電流をエミッタ抵抗器を介して負荷端に供給する出
力トランジスタのエミッタを増幅度の大なる差動増幅器
の一方の入力端子に接続し、上記負荷端の電圧に基準電
圧を加算して上記差動増幅器のもう一方の入力端子に接
続し、上記差動増幅器の出力端子を上記出力トランジス
タのベースに接続することにより、上記出力トランジス
タのコレクタ電流の最大値を制限することを特徴とする
出力トランジスタの電流制限回路。
The emitter of the output transistor that supplies the output current to the load end via the emitter resistor is connected to one input terminal of a differential amplifier with a high degree of amplification, and the reference voltage is added to the voltage at the load end to calculate the above difference. An output transistor configured to limit the maximum value of the collector current of the output transistor by connecting the output terminal of the differential amplifier to the other input terminal of the differential amplifier and connecting the output terminal of the differential amplifier to the base of the output transistor. current limiting circuit.
JP18715681U 1981-12-17 1981-12-17 Output transistor current limit circuit Pending JPS5893013U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18715681U JPS5893013U (en) 1981-12-17 1981-12-17 Output transistor current limit circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18715681U JPS5893013U (en) 1981-12-17 1981-12-17 Output transistor current limit circuit

Publications (1)

Publication Number Publication Date
JPS5893013U true JPS5893013U (en) 1983-06-23

Family

ID=29989726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18715681U Pending JPS5893013U (en) 1981-12-17 1981-12-17 Output transistor current limit circuit

Country Status (1)

Country Link
JP (1) JPS5893013U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54104761A (en) * 1978-02-03 1979-08-17 Nec Corp Audio amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54104761A (en) * 1978-02-03 1979-08-17 Nec Corp Audio amplifier

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