JPS599618U - transistor amplifier circuit - Google Patents
transistor amplifier circuitInfo
- Publication number
- JPS599618U JPS599618U JP10385782U JP10385782U JPS599618U JP S599618 U JPS599618 U JP S599618U JP 10385782 U JP10385782 U JP 10385782U JP 10385782 U JP10385782 U JP 10385782U JP S599618 U JPS599618 U JP S599618U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- npn
- base
- amplifier circuit
- transistor amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図、第３図は従来のトランジスタ増幅回路
、第４図は本考案の同増幅回路を示す。
主な図番の説明、３・・・負荷、９・・・入力端子、１
０・・・第１のＮＰＮ ）ランジスタ、１１・・・ＰＮ
Ｐ ）ランジスタ、１２・・・第２のＮＰＮ ）ランジ
スタ。1, 2, and 3 show a conventional transistor amplifier circuit, and FIG. 4 shows the same amplifier circuit according to the present invention. Explanation of main drawing numbers, 3...Load, 9...Input terminal, 1
0...first NPN) transistor, 11...PN
P) transistor, 12... second NPN) transistor.
Claims (1)
、第２のＮＰＮ トランジスタとより成るトランジスタ
増幅回路において、前記第１のＮＰＮ ）ランジスタの
コレクタとＰＮＰトランジスタのベースとを直結すると
共に該ＰＮＰ ）ランジスタのコレクタと第２のＮＰＮ
トランジスタのベースを直結し、前記第２のＮＰＮ ト
ランジスタのエミッタに負荷を接続し、前記第１のＮＰ
Ｎ ）ランジスタのベースに入力信号を印加し、前記第
２のＮＰＮ トランジスタのエミッタより出力を導出し
て前記負荷に供給し、前記３トランジスタにおける出力
残り電圧を減少させたことを特徴とするトランジスタ増
幅回路。In a transistor amplifier circuit comprising a first NPN transistor, a PNP transistor, and a second NPN transistor, the collector of the first NPN transistor is directly connected to the base of the PNP transistor, and the collector of the PNP transistor is directly connected to the base of the PNP transistor. and the second NPN
A load is connected to the emitter of the second NPN transistor, and the base of the first NPN transistor is directly connected to the base of the transistor.
N) A transistor amplifier characterized in that an input signal is applied to the base of the transistor, an output is derived from the emitter of the second NPN transistor and supplied to the load, and the remaining output voltage in the three transistors is reduced. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10385782U JPS599618U (en) | 1982-07-08 | 1982-07-08 | transistor amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10385782U JPS599618U (en) | 1982-07-08 | 1982-07-08 | transistor amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599618U true JPS599618U (en) | 1984-01-21 |
Family
ID=30244119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10385782U Pending JPS599618U (en) | 1982-07-08 | 1982-07-08 | transistor amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599618U (en) |
-
1982
- 1982-07-08 JP JP10385782U patent/JPS599618U/en active Pending
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