JPS6079820U - current mirror circuit - Google Patents
current mirror circuitInfo
- Publication number
- JPS6079820U JPS6079820U JP17260983U JP17260983U JPS6079820U JP S6079820 U JPS6079820 U JP S6079820U JP 17260983 U JP17260983 U JP 17260983U JP 17260983 U JP17260983 U JP 17260983U JP S6079820 U JPS6079820 U JP S6079820U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- collector
- base
- mirror circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は、従来の電流ミラー回路を示す回路
図、第３図は本考案の一実施例を示す回路図、及び第４
図は本考案の別の実施例を示す回路図である。
主な図番の説明、６・・・第１トランジスタ、７・・・
第２トランジスタ、８・・・第３トランジスタ、自。
１３・・・第４トランジスタ、１０．１４・・・第５ト
ランジスタ、１１・・・入力電流源。1 and 2 are circuit diagrams showing a conventional current mirror circuit, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention. Explanation of main figure numbers, 6...first transistor, 7...
Second transistor, 8...Third transistor, self. 13... Fourth transistor, 10.14... Fifth transistor, 11... Input current source.
Claims (1)
ンジスタと、該第１トランジスタのベースにエミッタが
、前記第１トランジスタのコレクタにベースがそれぞれ
接続された第３トランジスタと、前記第１トランジスタ
のコレクタに接続された入力電流源と、前記第３トラン
ジスタのエミッタ・コレクタ路に直列接続されたエミッ
タ・コレクタ路を有するダイオード接続された第４トラ
ンジスタと、前記第２トランジスタのベースとアースと
の間にエミッタ・コレクタ路が接続され、ベース及びエ
ミッタが前記第４トランジスタと共通接続された第５ト
ランジスタとから成り、前記入力電流源に流れる電流に
対応する出力電流を前記第２トランジスタのコレクタに
得る様にしたことを特徴とする電流ミラー回路。first and second transistors whose bases and emitters are commonly connected; a third transistor whose emitter is connected to the base of the first transistor; and whose base is connected to the collector of the first transistor; and a collector of the first transistor. a fourth diode-connected transistor having an emitter-collector path connected in series with the emitter-collector path of the third transistor, and between the base of the second transistor and ground; a fifth transistor having an emitter-collector path connected, the base and emitter of which are commonly connected to the fourth transistor, such that an output current corresponding to the current flowing through the input current source is obtained in the collector of the second transistor; A current mirror circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17260983U JPS6079820U (en) | 1983-11-07 | 1983-11-07 | current mirror circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17260983U JPS6079820U (en) | 1983-11-07 | 1983-11-07 | current mirror circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6079820U true JPS6079820U (en) | 1985-06-03 |
| JPH0238484Y2 JPH0238484Y2 (en) | 1990-10-17 |
Family
ID=30376217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17260983U Granted JPS6079820U (en) | 1983-11-07 | 1983-11-07 | current mirror circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079820U (en) |
-
1983
- 1983-11-07 JP JP17260983U patent/JPS6079820U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0238484Y2 (en) | 1990-10-17 |
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