JPS6074322U - current mirror circuit - Google Patents
current mirror circuitInfo
- Publication number
- JPS6074322U JPS6074322U JP16628283U JP16628283U JPS6074322U JP S6074322 U JPS6074322 U JP S6074322U JP 16628283 U JP16628283 U JP 16628283U JP 16628283 U JP16628283 U JP 16628283U JP S6074322 U JPS6074322 U JP S6074322U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current mirror
- mirror circuit
- collector
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は、従来の電流ミラー回路を示す回路
図、第３図は本考案の一実施例を示す回路図、及び第４
図は本考案の別の実施例を示す回路図である。
主な図番の説明、１０・・・・・・第１トランジスタ、
１１・・・・・・第２トランジスタ、１２・・・・・・
第３トランジスタ、１３・・・・・・第４トランジスタ
。1 and 2 are circuit diagrams showing a conventional current mirror circuit, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention. Explanation of main figure numbers, 10...first transistor,
11... Second transistor, 12...
Third transistor, 13... Fourth transistor.
Claims (1)
、該第１トランジスタのベース・コレクタ間に挿入され
るダイオード接続された第２トランジスタと、該第２ト
ランジスタと電流ミラー接続された第３トランジスタと
、該第３トランジスタによりベース電流路が形成される
第４トランジスタとから成り、前記入力電流源に流れる
入力電流に応じた出力電流を、前記第４トランジスタの
コレクタに得る様にした電流ミラー回路。a first transistor having a collector connected to an input current source; a second diode-connected transistor inserted between the base and collector of the first transistor; and a third transistor connected to the second transistor by a current mirror. and a fourth transistor whose base current path is formed by the third transistor, and the current mirror circuit is configured to obtain an output current corresponding to an input current flowing through the input current source to the collector of the fourth transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16628283U JPS6074322U (en) | 1983-10-26 | 1983-10-26 | current mirror circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16628283U JPS6074322U (en) | 1983-10-26 | 1983-10-26 | current mirror circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6074322U true JPS6074322U (en) | 1985-05-24 |
Family
ID=30364071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16628283U Pending JPS6074322U (en) | 1983-10-26 | 1983-10-26 | current mirror circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074322U (en) |
-
1983
- 1983-10-26 JP JP16628283U patent/JPS6074322U/en active Pending
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