JPS5978720U - current mirror circuit - Google Patents

current mirror circuit

Info

Publication number
JPS5978720U
JPS5978720U JP17519482U JP17519482U JPS5978720U JP S5978720 U JPS5978720 U JP S5978720U JP 17519482 U JP17519482 U JP 17519482U JP 17519482 U JP17519482 U JP 17519482U JP S5978720 U JPS5978720 U JP S5978720U
Authority
JP
Japan
Prior art keywords
current
transistor
mirror circuit
collector
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17519482U
Other languages
Japanese (ja)
Other versions
JPS636888Y2 (en
Inventor
寛次 田中
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP17519482U priority Critical patent/JPS5978720U/en
Publication of JPS5978720U publication Critical patent/JPS5978720U/en
Application granted granted Critical
Publication of JPS636888Y2 publication Critical patent/JPS636888Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来の電流ミラー回路を示す回路図、
及び第3図は本考案の一実施例を示す回路図である。 主な図番の説明、10・・・第1トランジスタ、11・
・・第2トランジスタ、12・・・第3トランジスタ、
16・・・第4トランジスタ、17・・・電流加算口路
Figures 1 and 2 are circuit diagrams showing conventional current mirror circuits,
and FIG. 3 are circuit diagrams showing one embodiment of the present invention. Explanation of main figure numbers, 10... first transistor, 11...
...Second transistor, 12...Third transistor,
16... Fourth transistor, 17... Current adding port.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タイオード接続された第1トランジスタと、該第1トラ
ンジスタと電流ミラー関係に接続された第2トランジス
タと、ベース及びエミッタが前記第2トランジスタと共
通接続された第3トランジスタと、前記第1トランジス
タに所定の電流を流す様に接続された入力電流源と、該
入力電流源に流れる電流と等しい電流を流す第4トラン
ジスタと、前記第3トランジスタのコレクタ電流と第4
トランジスタのコレクタ電流との差電洸を前記第2トラ
ンジスタのコレクタ電流に加算する手段とから成り、前
記第2トランジスタのコレクタに接続された出力端子に
、前記入力電流源に流れる電流と略等しい電流を得る様
にしたことを特徴とする電流ミラー回路。
a first transistor connected in a diode manner; a second transistor connected in a current mirror relationship with the first transistor; a third transistor whose base and emitter are commonly connected to the second transistor; an input current source connected to flow a current equal to the current flowing through the input current source; a fourth transistor that flows a current equal to the current flowing through the input current source;
means for adding a difference in current from the collector current of the transistor to the collector current of the second transistor, and a current substantially equal to the current flowing through the input current source is supplied to an output terminal connected to the collector of the second transistor. A current mirror circuit characterized in that it obtains the following.
JP17519482U 1982-11-18 1982-11-18 current mirror circuit Granted JPS5978720U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17519482U JPS5978720U (en) 1982-11-18 1982-11-18 current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17519482U JPS5978720U (en) 1982-11-18 1982-11-18 current mirror circuit

Publications (2)

Publication Number Publication Date
JPS5978720U true JPS5978720U (en) 1984-05-28
JPS636888Y2 JPS636888Y2 (en) 1988-02-27

Family

ID=30381211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17519482U Granted JPS5978720U (en) 1982-11-18 1982-11-18 current mirror circuit

Country Status (1)

Country Link
JP (1) JPS5978720U (en)

Also Published As

Publication number Publication date
JPS636888Y2 (en) 1988-02-27

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