JPS6039126U - current source circuit - Google Patents
current source circuitInfo
- Publication number
- JPS6039126U JPS6039126U JP13069683U JP13069683U JPS6039126U JP S6039126 U JPS6039126 U JP S6039126U JP 13069683 U JP13069683 U JP 13069683U JP 13069683 U JP13069683 U JP 13069683U JP S6039126 U JPS6039126 U JP S6039126U
- Authority
- JP
- Japan
- Prior art keywords
- current
- mirror circuit
- current mirror
- source circuit
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Electrical Variables (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の定電流回路の一例を示す回路図、第２図
は本考案による一実施例を示す回路図−である。
第１図、第２図において、１・・・電源、３・・・出力
端子、１０・・・電流切換端子、２． ４． ５． ７
． １１．１３・・・トランジスタ、６，８・・・ダイ
オード、９．１２・・・抵抗をそれぞれ示す。FIG. 1 is a circuit diagram showing an example of a conventional constant current circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 and 2, 1...power supply, 3...output terminal, 10...current switching terminal, 2. 4. 5. 7
．． 11.13...transistor, 6,8...diode, 9.12...resistance, respectively.
Claims (1)
カレントミラー回路と、入力電流に応じて出力端子から
電流を引き込み互いの入力端子が並列に接続された第２
および第３のカレントミラー回路と、該第１および第２
のカレントミラー回路の入力端子間を結合する手段と、
前記第３のカレントミラー回路の出力電流に応答して前
記第１のカレントミラー回路を遮断する手段と、前記第
２および第３のカレントミラー回路を遮断する手段とを
備えることを特徴とする電流源回路。, a first current mirror circuit that flows current to the output terminal according to the input current, and a second current mirror circuit that draws current from the output terminal according to the input current and whose input terminals are connected in parallel.
and a third current mirror circuit;
means for coupling between the input terminals of the current mirror circuit;
A current comprising means for interrupting the first current mirror circuit in response to an output current of the third current mirror circuit, and means for interrupting the second and third current mirror circuits. source circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13069683U JPS6039126U (en) | 1983-08-24 | 1983-08-24 | current source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13069683U JPS6039126U (en) | 1983-08-24 | 1983-08-24 | current source circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6039126U true JPS6039126U (en) | 1985-03-18 |
| JPH0413696Y2 JPH0413696Y2 (en) | 1992-03-30 |
Family
ID=30295727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13069683U Granted JPS6039126U (en) | 1983-08-24 | 1983-08-24 | current source circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039126U (en) |
-
1983
- 1983-08-24 JP JP13069683U patent/JPS6039126U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0413696Y2 (en) | 1992-03-30 |
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