JPS59183037U - transistor output circuit - Google Patents

transistor output circuit

Info

Publication number
JPS59183037U
JPS59183037U JP7746883U JP7746883U JPS59183037U JP S59183037 U JPS59183037 U JP S59183037U JP 7746883 U JP7746883 U JP 7746883U JP 7746883 U JP7746883 U JP 7746883U JP S59183037 U JPS59183037 U JP S59183037U
Authority
JP
Japan
Prior art keywords
output circuit
transistor
transistor output
output
saturation voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7746883U
Other languages
Japanese (ja)
Inventor
後藤 三郎
Original Assignee
富士電機株式会社
富士フアコム制御株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社, 富士フアコム制御株式会社 filed Critical 富士電機株式会社
Priority to JP7746883U priority Critical patent/JPS59183037U/en
Publication of JPS59183037U publication Critical patent/JPS59183037U/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

7第1図は従来のダーリントン接続トランジスタ出力回
路の構成を示す回路図、第2図は本考案によるダーリン
トン接続トランジスタ出力回路の構成例を示す回路図で
ある。− 1・・・ダーリントン接続トランジスタ、2・・・抵抗
、3・・・負荷、4・・・負荷用電源、5・・・エミッ
タバイアス’IIE源、6. 7−・・トランジスタ。
7. FIG. 1 is a circuit diagram showing the configuration of a conventional Darlington-connected transistor output circuit, and FIG. 2 is a circuit diagram showing an example of the configuration of the Darlington-connected transistor output circuit according to the present invention. - 1... Darlington connected transistor, 2... Resistor, 3... Load, 4... Load power supply, 5... Emitter bias 'IIE source, 6. 7-...Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トランジスタ出力回路を構成するトランジスタのエミッ
タと接地電位間に該トランジスタの出力飽和電圧とは逆
極性の電圧源を接続することにより、出力飽和電圧を相
殺したことを特徴とするトランジスタ出力回路。
1. A transistor output circuit, characterized in that the output saturation voltage of the transistor is canceled by connecting a voltage source having a polarity opposite to that of the output saturation voltage of the transistor between the emitter of the transistor constituting the transistor output circuit and a ground potential.
JP7746883U 1983-05-25 1983-05-25 transistor output circuit Pending JPS59183037U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7746883U JPS59183037U (en) 1983-05-25 1983-05-25 transistor output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7746883U JPS59183037U (en) 1983-05-25 1983-05-25 transistor output circuit

Publications (1)

Publication Number Publication Date
JPS59183037U true JPS59183037U (en) 1984-12-06

Family

ID=30207495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7746883U Pending JPS59183037U (en) 1983-05-25 1983-05-25 transistor output circuit

Country Status (1)

Country Link
JP (1) JPS59183037U (en)

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