JPS61191615U - - Google Patents
Info
- Publication number
- JPS61191615U JPS61191615U JP7600085U JP7600085U JPS61191615U JP S61191615 U JPS61191615 U JP S61191615U JP 7600085 U JP7600085 U JP 7600085U JP 7600085 U JP7600085 U JP 7600085U JP S61191615 U JPS61191615 U JP S61191615U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- transistor
- amplifier
- circuit
- control pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は従来例を示す回路図である。
２……増幅器、６……ＮＰＮトランジスタ、８
……ＰＮＰトランジスタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing a conventional example. 2...Amplifier, 6...NPN transistor, 8
...PNP transistor.
Claims (1)
た抵抗体と、第１のミユーテイング用トランジス
タとを有し、上記抵抗体と上記第１のミユーテイ
ング用トランジスタとで分圧回路を構成し、該分
圧回路の分圧点を出力端子とし、上記第１のミユ
ーテイング用トランジスタに第１のミユーテイン
グ制御パルスを加える手段を有する増幅器のミユ
ーテイング回路において、上記第１のミユーテイ
ング用トランジスタに並列に上記第１のミユーテ
イング用トランジスタと導電型の異なる第２のミ
ユーテイング用トランジスタを接続し、上記第２
のミユーテイング用トランジスタに上記第１のミ
ユーテイング制御パルスと逆極性の第２のミユー
テイング制御パルスを上記第１のミユーテイング
制御パルスと同時に加えることを特徴とする増幅
器のミユーテイング回路。 It has an amplifier, a resistor connected in series to the output terminal of the amplifier, and a first muting transistor, and the resistor and the first muting transistor constitute a voltage dividing circuit. The muting circuit of the amplifier has a voltage dividing point of the voltage circuit as an output terminal and means for applying a first muting control pulse to the first muting transistor. A mutating transistor and a second muting transistor having different conductivity types are connected, and the above-mentioned second mutating transistor is
A muting circuit for an amplifier, characterized in that a second muting control pulse having a polarity opposite to that of the first muting control pulse is simultaneously applied to the muting transistor of the amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7600085U JPS61191615U (en) | 1985-05-22 | 1985-05-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7600085U JPS61191615U (en) | 1985-05-22 | 1985-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61191615U true JPS61191615U (en) | 1986-11-28 |
Family
ID=30617734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7600085U Pending JPS61191615U (en) | 1985-05-22 | 1985-05-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61191615U (en) |
-
1985
- 1985-05-22 JP JP7600085U patent/JPS61191615U/ja active Pending