JPS61174229U - - Google Patents

Info

Publication number
JPS61174229U
JPS61174229U JP5598485U JP5598485U JPS61174229U JP S61174229 U JPS61174229 U JP S61174229U JP 5598485 U JP5598485 U JP 5598485U JP 5598485 U JP5598485 U JP 5598485U JP S61174229 U JPS61174229 U JP S61174229U
Authority
JP
Japan
Prior art keywords
transistor
base
resistors
conductive
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5598485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5598485U priority Critical patent/JPS61174229U/ja
Publication of JPS61174229U publication Critical patent/JPS61174229U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例によるトランジスタ
スイツチング回路の接続図、第2図は従来のトラ
ンジスタスイツチング回路の接続図である。 1……信号源、2……入力端子、3,6,13
……抵抗、4……出力端子、5,11……トラン
ジスタ、14……コントロール端子、15……電
源、16……録音再生切換え出力端子。
FIG. 1 is a connection diagram of a transistor switching circuit according to an embodiment of the present invention, and FIG. 2 is a connection diagram of a conventional transistor switching circuit. 1... Signal source, 2... Input terminal, 3, 6, 13
...Resistor, 4...Output terminal, 5, 11...Transistor, 14...Control terminal, 15...Power supply, 16...Recording/playback switching output terminal.

Claims (1)

【実用新案登録請求の範囲】 (1) エミツタが電源に接続された第1のトラン
ジスタと、エミツタがアースに接続された第2の
トランジスタを備え、前記第1のトランジスタの
ベース・エミツタ間に第1の抵抗を接続し、該第
1のトランジスタのベースと第2のトランジスタ
のベースを第2及び第3の抵抗の直列回路で第3
の抵抗が第2のトランジスタのベースに接続され
るよう接続し、前記第2及び第3の抵抗の接続点
をアースすることにより第1のトランジスタを導
通させ、アースしない場合、第1のトランジスタ
は導通せず、第2のトランジスタのみが導通する
よう第1及び第2、第3の抵抗の値を選定してな
るトランジスタスイツチング回路。 (2) 第2のトランジスタを信号の減衰を目的と
して使用した実用新案登録請求の範囲第1項記載
のトランジスタスイツチング回路。
[Claims for Utility Model Registration] (1) A first transistor whose emitter is connected to a power source, and a second transistor whose emitter is connected to ground, and a transistor between the base and emitter of the first transistor. 1 resistor is connected, and the base of the first transistor and the base of the second transistor are connected to a third resistor through a series circuit of second and third resistors.
is connected to the base of the second transistor, and the connection point of the second and third resistors is grounded to make the first transistor conductive. If the first transistor is not grounded, the first transistor is A transistor switching circuit in which the values of the first, second, and third resistors are selected so that only the second transistor is conductive and not conductive. (2) The transistor switching circuit according to claim 1, which uses a second transistor for the purpose of attenuating a signal.
JP5598485U 1985-04-15 1985-04-15 Pending JPS61174229U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5598485U JPS61174229U (en) 1985-04-15 1985-04-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5598485U JPS61174229U (en) 1985-04-15 1985-04-15

Publications (1)

Publication Number Publication Date
JPS61174229U true JPS61174229U (en) 1986-10-30

Family

ID=30579167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5598485U Pending JPS61174229U (en) 1985-04-15 1985-04-15

Country Status (1)

Country Link
JP (1) JPS61174229U (en)

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