JPS6126350U - stereo indicator circuit - Google Patents
stereo indicator circuitInfo
- Publication number
- JPS6126350U JPS6126350U JP11092084U JP11092084U JPS6126350U JP S6126350 U JPS6126350 U JP S6126350U JP 11092084 U JP11092084 U JP 11092084U JP 11092084 U JP11092084 U JP 11092084U JP S6126350 U JPS6126350 U JP S6126350U
- Authority
- JP
- Japan
- Prior art keywords
- switching transistor
- indicator circuit
- stereo
- stereo indicator
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のステレオインジケータ回路の構成を示
す図、第２図は同、電源オン直後の各部の電圧波形図、
第３図は従来のステレオインジケータ回路の構成を示す
図、第４図は同、電源オン直後の各部の電圧波形図であ
る。
７は入力端子、８は第１の抵抗、９，１０は第１、第２
のスイッチングトランジスタ、１．１．１２は第２、第
３の抵抗、１４は電源、１５．１６は第１、第２の出力
端子、１７はコンデンサ。Fig. 1 is a diagram showing the configuration of the stereo indicator circuit of the present invention, and Fig. 2 is a voltage waveform diagram of each part immediately after the power is turned on.
FIG. 3 is a diagram showing the configuration of a conventional stereo indicator circuit, and FIG. 4 is a diagram of voltage waveforms at various parts immediately after the power is turned on. 7 is an input terminal, 8 is a first resistor, 9 and 10 are first and second resistors.
1.1.12 are second and third resistors, 14 is a power supply, 15.16 are first and second output terminals, and 17 is a capacitor.
Claims (1)
の抵抗８を介して接地するとともに、エミツタを接地し
た第１のスイッチングトランジスタ９のベースに接続し
、当該第１のスイッチングトランジスタ９のコレクタを
第２の抵抗１１を介して電源１４に接続するとともに、
エミツタを接地した第２のスイッチングトランジスタ１
０のベースに接続し、当該第２のスイッチングトランジ
スタ１０のコレクタを第３の抵抗１２、ステレオインジ
ケータ１３を介して上記電源１４に接続した構成におい
て、上記入力端子７をコンデンサ１７を介して上記電源
１４に接続したことを特徴とするステレオインジケータ
回路。Input terminal 7, where the stereo/mono switching signal is input, is the first input terminal.
The emitter is connected to the base of the first switching transistor 9 which is grounded, and the collector of the first switching transistor 9 is connected to the power supply 14 via the second resistor 11. ,
Second switching transistor 1 whose emitter is grounded
0, and the collector of the second switching transistor 10 is connected to the power source 14 through the third resistor 12 and the stereo indicator 13, and the input terminal 7 is connected to the power source 14 through the capacitor 17. A stereo indicator circuit characterized in that it is connected to 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11092084U JPS6126350U (en) | 1984-07-21 | 1984-07-21 | stereo indicator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11092084U JPS6126350U (en) | 1984-07-21 | 1984-07-21 | stereo indicator circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6126350U true JPS6126350U (en) | 1986-02-17 |
Family
ID=30670037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11092084U Pending JPS6126350U (en) | 1984-07-21 | 1984-07-21 | stereo indicator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6126350U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5813644U (en) * | 1981-07-20 | 1983-01-28 | 日本電気ホームエレクトロニクス株式会社 | temperature fuse |
-
1984
- 1984-07-21 JP JP11092084U patent/JPS6126350U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5813644U (en) * | 1981-07-20 | 1983-01-28 | 日本電気ホームエレクトロニクス株式会社 | temperature fuse |
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