JPS59161716U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS59161716U
JPS59161716U JP5615683U JP5615683U JPS59161716U JP S59161716 U JPS59161716 U JP S59161716U JP 5615683 U JP5615683 U JP 5615683U JP 5615683 U JP5615683 U JP 5615683U JP S59161716 U JPS59161716 U JP S59161716U
Authority
JP
Japan
Prior art keywords
circuit
muting
muting circuit
transistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5615683U
Other languages
Japanese (ja)
Inventor
俊一 浜舘
節郎 川崎
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP5615683U priority Critical patent/JPS59161716U/en
Publication of JPS59161716U publication Critical patent/JPS59161716U/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来のミューティング回路の構成図と
それのミューティングオフ時の出力波形図、第3図、第
4図はこの考案に係をるミューティング回路の一実施例
を示す構成図とそれの作用を説明するための交流等価回
路図である。 IN・・・入力端、OUT・・・出力端、R1−R6・
・・抵抗、C・・・コンデンサ、Q1+ 02・・・ト
ランジスタ、M−IN・・・ミューティング電圧入力端
Figures 1 and 2 show the configuration of a conventional muting circuit and its output waveform when muting is off, and Figures 3 and 4 show an embodiment of the muting circuit according to this invention. FIG. 2 is an AC equivalent circuit diagram for explaining the configuration diagram shown and its operation. IN...Input end, OUT...Output end, R1-R6.
...Resistor, C...Capacitor, Q1+02...Transistor, M-IN...Muting voltage input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベース回路に供給されるミューティング電圧の有無によ
りコレクターエミッタ回路を介して信号線路を実質的に
遮断または導通状態とするトランジスタを有してなるミ
ューティング回路において、前記トランジスタのベース
回路にミューティングオフ状態で高出力インピーダンス
を呈する回路素子を挿入したことを特徴とするミューテ
ィング回路・
In a muting circuit comprising a transistor that substantially cuts off or conducts a signal line through a collector emitter circuit depending on the presence or absence of a muting voltage supplied to the base circuit, the muting circuit is applied to the base circuit of the transistor to turn off the muting circuit. A muting circuit characterized by inserting a circuit element that exhibits high output impedance in the state
JP5615683U 1983-04-15 1983-04-15 Muting circuit Pending JPS59161716U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5615683U JPS59161716U (en) 1983-04-15 1983-04-15 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5615683U JPS59161716U (en) 1983-04-15 1983-04-15 Muting circuit

Publications (1)

Publication Number Publication Date
JPS59161716U true JPS59161716U (en) 1984-10-30

Family

ID=30186477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5615683U Pending JPS59161716U (en) 1983-04-15 1983-04-15 Muting circuit

Country Status (1)

Country Link
JP (1) JPS59161716U (en)

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