JPS60193715U - Pulse polarity designation circuit - Google Patents

Pulse polarity designation circuit

Info

Publication number
JPS60193715U
JPS60193715U JP8147484U JP8147484U JPS60193715U JP S60193715 U JPS60193715 U JP S60193715U JP 8147484 U JP8147484 U JP 8147484U JP 8147484 U JP8147484 U JP 8147484U JP S60193715 U JPS60193715 U JP S60193715U
Authority
JP
Japan
Prior art keywords
pulse
transistor
polarity
designation circuit
pulse polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8147484U
Other languages
Japanese (ja)
Inventor
谷合　利夫
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP8147484U priority Critical patent/JPS60193715U/en
Publication of JPS60193715U publication Critical patent/JPS60193715U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１，２図は、それぞれこの考案のパルス極性指定回路
の一実施例を示す回路図及び入力パルスの波形を示す信
号波形図である。 １・・・パルス極性指定回路、２・・・入力端子、３・
・・出力端子、Ｑｌ・・・第１のトランジスタ、Ｑ２・
・・第２のトランジスタ。1 and 2 are a circuit diagram showing an embodiment of the pulse polarity specifying circuit of this invention and a signal waveform diagram showing the waveform of an input pulse, respectively. 1...Pulse polarity designation circuit, 2...Input terminal, 3...
...output terminal, Ql...first transistor, Q2.
...Second transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 正極性又は負極性のパルスが印加される入力端子と、こ
の入力端子にベースが接続され、前記正極性パルスの印
加により導通する第１のトランジスタと、前記入力端子
にエミッタが接続され、前記負極性パルスの印加により
導通する第２のトランジスタと、この第２のトランジス
タ及び前記第１のトランジスタのコレクタに共通接続し
た出力端子とを具備するパルス極性指定回路。an input terminal to which a pulse of positive polarity or negative polarity is applied; a first transistor whose base is connected to this input terminal and becomes conductive when the positive pulse is applied; and a first transistor whose emitter is connected to the input terminal and which is connected to the negative terminal. 1. A pulse polarity designation circuit comprising: a second transistor that becomes conductive upon application of a polarity pulse; and an output terminal commonly connected to collectors of the second transistor and the first transistor.
JP8147484U 1984-05-31 1984-05-31 Pulse polarity designation circuit Pending JPS60193715U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8147484U JPS60193715U (en) 1984-05-31 1984-05-31 Pulse polarity designation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8147484U JPS60193715U (en) 1984-05-31 1984-05-31 Pulse polarity designation circuit

Publications (1)

Publication Number Publication Date
JPS60193715U true JPS60193715U (en) 1985-12-23

Family

ID=30628288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8147484U Pending JPS60193715U (en) 1984-05-31 1984-05-31 Pulse polarity designation circuit

Country Status (1)

Country Link
JP (1) JPS60193715U (en)

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