JPS5811332U - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPS5811332U
JPS5811332U JP10360181U JP10360181U JPS5811332U JP S5811332 U JPS5811332 U JP S5811332U JP 10360181 U JP10360181 U JP 10360181U JP 10360181 U JP10360181 U JP 10360181U JP S5811332 U JPS5811332 U JP S5811332U
Authority
JP
Japan
Prior art keywords
waveform shaping
shaping circuit
output signal
circuit
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10360181U
Other languages
Japanese (ja)
Other versions
JPH028442Y2 (en
Inventor
興津　裕己
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP10360181U priority Critical patent/JPS5811332U/en
Publication of JPS5811332U publication Critical patent/JPS5811332U/en
Application granted granted Critical
Publication of JPH028442Y2 publication Critical patent/JPH028442Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の波形整形回路の説明に供する線図、第２
図は本考案による波形回路の一実施例を示す接続図、第
３図は第２図例の説明に供する線図である。 １は入力端子、２はピーク検波回路、５はレベル比較回
路、１０は出力端子である。Figure 1 is a diagram used to explain a conventional waveform shaping circuit;
The figure is a connection diagram showing one embodiment of the waveform circuit according to the present invention, and FIG. 3 is a diagram for explaining the example in FIG. 1 is an input terminal, 2 is a peak detection circuit, 5 is a level comparison circuit, and 10 is an output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号をピーク検波するピーク検波回路と、この入力
信号のレベル比較をするレベル比較回路とを備え、上記
ピーク検波回路の出力信号を上記レベル比較回路に基準
電圧として供給し、上記レベル比較回路より出力信号を
得る様にした波形整形回路。The output signal of the peak detection circuit is supplied as a reference voltage to the level comparison circuit, and the output signal of the peak detection circuit is supplied as a reference voltage to the level comparison circuit. A waveform shaping circuit designed to obtain an output signal.
JP10360181U 1981-07-13 1981-07-13 Waveform shaping circuit Granted JPS5811332U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10360181U JPS5811332U (en) 1981-07-13 1981-07-13 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10360181U JPS5811332U (en) 1981-07-13 1981-07-13 Waveform shaping circuit

Publications (2)

Publication Number Publication Date
JPS5811332U true JPS5811332U (en) 1983-01-25
JPH028442Y2 JPH028442Y2 (en) 1990-02-28

Family

ID=29898210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10360181U Granted JPS5811332U (en) 1981-07-13 1981-07-13 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPS5811332U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125054A (en) * 1974-08-26 1976-03-01 Nippon Steel Corp SHINGOHAKEIHIZUMI HOSEIKAIRO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125054A (en) * 1974-08-26 1976-03-01 Nippon Steel Corp SHINGOHAKEIHIZUMI HOSEIKAIRO

Also Published As

Publication number Publication date
JPH028442Y2 (en) 1990-02-28

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