JPS5857918U - Highest point holding circuit - Google Patents

Highest point holding circuit

Info

Publication number
JPS5857918U
JPS5857918U JP15306881U JP15306881U JPS5857918U JP S5857918 U JPS5857918 U JP S5857918U JP 15306881 U JP15306881 U JP 15306881U JP 15306881 U JP15306881 U JP 15306881U JP S5857918 U JPS5857918 U JP S5857918U
Authority
JP
Japan
Prior art keywords
holding circuit
highest point
point holding
integrator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15306881U
Other languages
Japanese (ja)
Inventor
晝馬 俊治
相川 正樹
Original Assignee
株式会社横河電機製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社横河電機製作所 filed Critical 株式会社横河電機製作所
Priority to JP15306881U priority Critical patent/JPS5857918U/en
Publication of JPS5857918U publication Critical patent/JPS5857918U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を示す電気的接続図、第2
図は本考の他の実施例を示す電気的接続図である。 1.3・・・比較器、2・・・積分器、Dl、 D2・
・・ダイオ−11C・・・キャパシタ、SW1〜SW3
・・・スイッチ。
Fig. 1 is an electrical connection diagram showing one embodiment of the present invention;
The figure is an electrical connection diagram showing another embodiment of the present invention. 1.3...Comparator, 2...Integrator, Dl, D2・
...Diode-11C...Capacitor, SW1-SW3
···switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号をその一方の入力に受ける比較器と、該比較器
の出力にそのカソード側が接続されたダイオードと、該
ダイオードの両側を強制的に同電位にする手段と、該ダ
イオードのアノード側がその入力に接続された積分器と
で構成され、該積分器の出力が前記比較器の他方の入力
に帰還されると共に積分器の出力をその出力とする最高
点保持回路。
a comparator receiving an input signal at one input; a diode having its cathode connected to the output of the comparator; means for forcing both sides of the diode to have the same potential; an integrator connected to the integrator, the output of the integrator is fed back to the other input of the comparator, and the output of the integrator is used as its output.
JP15306881U 1981-10-15 1981-10-15 Highest point holding circuit Pending JPS5857918U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15306881U JPS5857918U (en) 1981-10-15 1981-10-15 Highest point holding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15306881U JPS5857918U (en) 1981-10-15 1981-10-15 Highest point holding circuit

Publications (1)

Publication Number Publication Date
JPS5857918U true JPS5857918U (en) 1983-04-19

Family

ID=29945696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15306881U Pending JPS5857918U (en) 1981-10-15 1981-10-15 Highest point holding circuit

Country Status (1)

Country Link
JP (1) JPS5857918U (en)

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