JPS6061820U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS6061820U JPS6061820U JP15468183U JP15468183U JPS6061820U JP S6061820 U JPS6061820 U JP S6061820U JP 15468183 U JP15468183 U JP 15468183U JP 15468183 U JP15468183 U JP 15468183U JP S6061820 U JPS6061820 U JP S6061820U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- muting
- transistor
- main power
- muting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のミューティング回路を示す図、第２図は
第１図の各部波形を示す図、第３図は本考案による一実
施例、第４図は第３図の各部波形を示す図、第５図及び
第６図は本考案による他の実施例を示す図である。
１・・・・・・増幅器、２・・・・・・ミューティング
端子、３・・・・・・サブ電源、４・・・・・・メイン
電源、５・・・・・・リレー信号、Ｑｌ・・・・・・ミ
ューティング用トランジスタ、Ｃ１〜Ｃ５・・・・・・
コンデンサ、ＤＩ’、Ｄ２・・・・・・ダイオード、Ｄ
３・・・・・・ツェナーダイオード。Fig. 1 is a diagram showing a conventional muting circuit, Fig. 2 is a diagram showing waveforms of various parts of Fig. 1, Fig. 3 is an embodiment according to the present invention, and Fig. 4 is a diagram showing waveforms of various parts of Fig. 3. 5 and 6 are diagrams showing other embodiments of the present invention. 1...Amplifier, 2...Muting terminal, 3...Sub power supply, 4...Main power supply, 5...Relay signal, Ql... Muting transistor, C1 to C5...
Capacitor, DI', D2...Diode, D
3...Zener diode.
Claims (1)
メン電源によって制御され出力されるリレー信号と、前
記リレー信号のレベルに応じてＯＮ・ＯＦＦ制御される
第１のトランジスタと前記トランジスタのＯＮ・ＯＦＦ
にミューティングを行う第２のトランジスタとを備え、
サブ電源及びメイン電源のＯＮ・ＯＦＦに応じてミュー
ティングを行うようにしたことを特徴とするミューティ
ング回路。In an amplifier equipped with a main power supply and a sub power supply, a relay signal controlled and outputted by the main power supply, a first transistor whose ON/OFF is controlled according to the level of the relay signal, and ON/OFF of the transistor.
and a second transistor that performs muting,
A muting circuit characterized in that muting is performed in response to ON/OFF of a sub power supply and a main power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15468183U JPS6061820U (en) | 1983-10-05 | 1983-10-05 | Muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15468183U JPS6061820U (en) | 1983-10-05 | 1983-10-05 | Muting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6061820U true JPS6061820U (en) | 1985-04-30 |
Family
ID=30341848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15468183U Pending JPS6061820U (en) | 1983-10-05 | 1983-10-05 | Muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6061820U (en) |
-
1983
- 1983-10-05 JP JP15468183U patent/JPS6061820U/en active Pending
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