JPS6232636U - - Google Patents
Info
- Publication number
- JPS6232636U JPS6232636U JP12421985U JP12421985U JPS6232636U JP S6232636 U JPS6232636 U JP S6232636U JP 12421985 U JP12421985 U JP 12421985U JP 12421985 U JP12421985 U JP 12421985U JP S6232636 U JPS6232636 U JP S6232636U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- emitter
- collector
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案に係る実施例を示す回路図、第
２図は従来例を示す回路図である。
２０……信号入力端子、２１……第１の信号出
力端子、２２……第２の信号出力端子、Ｔｒ１１
……第１のトランジスタ、Ｔｒ１２……第２のト
ラスジスタ、Ｔｒ１３……第３のトランジスタ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 20... Signal input terminal, 21... First signal output terminal, 22... Second signal output terminal, Tr 11
...first transistor, Tr 12 ... second transistor, Tr 13 ... third transistor.
Claims (1)
子、及び第１ないし第３のトランジスタを備え、 第１のトランジスタのエミツタを上記信号入力
端子に接続し、コレクタを上記第２の信号出力端
子に接続するとともに、ベースにバイアス電圧を
供給し、 第２のトランジスタのエミツタを上記信号入力
端子に接続するとともに、ベースも上記第１のト
ラスジスタのベースに接続し、 第３のトランジスタのベースを上記第２のトラ
ンジスタのコレクタに接続し、コレクタを上記第
１の信号出力端子に接続するとともに、エミツタ
を接地して成ることを特徹とする切換回路。[Claims for Utility Model Registration] - comprises a signal input terminal, first and second signal output terminals, and first to third transistors, and the emitter of the first transistor is connected to the signal input terminal. , the collector is connected to the second signal output terminal, a bias voltage is supplied to the base, the emitter of the second transistor is connected to the signal input terminal, and the base is also connected to the base of the first transistor. A switching circuit characterized in that the base of the third transistor is connected to the collector of the second transistor, the collector is connected to the first signal output terminal, and the emitter is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12421985U JPH0419855Y2 (en) | 1985-08-13 | 1985-08-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12421985U JPH0419855Y2 (en) | 1985-08-13 | 1985-08-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6232636U true JPS6232636U (en) | 1987-02-26 |
| JPH0419855Y2 JPH0419855Y2 (en) | 1992-05-07 |
Family
ID=31016031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12421985U Expired JPH0419855Y2 (en) | 1985-08-13 | 1985-08-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419855Y2 (en) |
-
1985
- 1985-08-13 JP JP12421985U patent/JPH0419855Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0419855Y2 (en) | 1992-05-07 |
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