JPH0172715U - - Google Patents
Info
- Publication number
- JPH0172715U JPH0172715U JP1987167764U JP16776487U JPH0172715U JP H0172715 U JPH0172715 U JP H0172715U JP 1987167764 U JP1987167764 U JP 1987167764U JP 16776487 U JP16776487 U JP 16776487U JP H0172715 U JPH0172715 U JP H0172715U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- base
- whose
- bias voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例であるエミツタホロ
ア回路１９の構成を示す回路図、第２図は従来技
術のエミツタホロア回路９の構成を示す回路図で
ある。
１２，１３，１４，１６……トランジスタ、１
１……定電流源、１７……バイアス電圧発生器。
FIG. 1 is a circuit diagram showing the configuration of an emitter follower circuit 19 according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of an emitter follower circuit 9 of the prior art. 12, 13, 14, 16...transistor, 1
1... Constant current source, 17... Bias voltage generator.
Claims (1)
端子に接続された第１のトランジスタと、 第１のトランジスタのコレクタとエミツタとに
亘つて設けられ、ベースにバイアス電圧が印加さ
れる第２のトランジスタが介在される帰還回路と
を含むことを特徴とする入力回路。[Claims for Utility Model Registration] A first transistor whose base is connected to the input terminal and whose emitter is connected to the output terminal, and a bias voltage applied to the base is provided across the collector and emitter of the first transistor. and a feedback circuit in which a second transistor is interposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16776487U JPH0614498Y2 (en) | 1987-10-31 | 1987-10-31 | Input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16776487U JPH0614498Y2 (en) | 1987-10-31 | 1987-10-31 | Input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0172715U true JPH0172715U (en) | 1989-05-16 |
| JPH0614498Y2 JPH0614498Y2 (en) | 1994-04-13 |
Family
ID=31456351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16776487U Expired - Lifetime JPH0614498Y2 (en) | 1987-10-31 | 1987-10-31 | Input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0614498Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358547A (en) * | 2000-06-12 | 2001-12-26 | Fujitsu Quantum Devices Ltd | Buffer circuit |
-
1987
- 1987-10-31 JP JP16776487U patent/JPH0614498Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358547A (en) * | 2000-06-12 | 2001-12-26 | Fujitsu Quantum Devices Ltd | Buffer circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0614498Y2 (en) | 1994-04-13 |