JPS5967019U - bias circuit - Google Patents

bias circuit

Info

Publication number
JPS5967019U
JPS5967019U JP16023382U JP16023382U JPS5967019U JP S5967019 U JPS5967019 U JP S5967019U JP 16023382 U JP16023382 U JP 16023382U JP 16023382 U JP16023382 U JP 16023382U JP S5967019 U JPS5967019 U JP S5967019U
Authority
JP
Japan
Prior art keywords
circuit
bias circuit
bias
voltage
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16023382U
Other languages
Japanese (ja)
Other versions
JPS631455Y2 (en
Inventor
大嶋　俊壽
山口　富士夫
福田　督也
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP16023382U priority Critical patent/JPS5967019U/en
Publication of JPS5967019U publication Critical patent/JPS5967019U/en
Application granted granted Critical
Publication of JPS631455Y2 publication Critical patent/JPS631455Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のバイアス回路からなる差動増幅器の回路
図、第２図はこの考案のバイアス回路を適用した差動増
幅器の回路図、第３図はこの考案のバイアス回路をゲイ
ンコントロール回路に応用した回路図を示す。 図中、Ｑ５〜Ｑ９はトランジスタ、Ｄ□〜９３はダイオ
ード、Ｒ６〜Ｒ□２は抵抗、Ｖｃｏは電源電圧を示す。Figure 1 is a circuit diagram of a differential amplifier consisting of a conventional bias circuit, Figure 2 is a circuit diagram of a differential amplifier to which the bias circuit of this invention is applied, and Figure 3 is a circuit diagram of a differential amplifier using the bias circuit of this invention as a gain control circuit. The applied circuit diagram is shown. In the figure, Q5 to Q9 are transistors, D□ to 93 are diodes, R6 to R□2 are resistors, and Vco is a power supply voltage.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一方の入力端にバイアスを設定する電圧が供給されてい
る差動増幅回路の出力端を、エミッタホロワ接続された
帰還用トランジスタ、及びＮ接合部を介して、他方の入
力端に接続し、かつ前記出力端の電圧をさらにエミッタ
ホロワトランジスタを介して電子回路の電流源となるカ
レントミラ回路に供給することを特徴とするバイアス回
路。The output terminal of a differential amplifier circuit, whose one input terminal is supplied with a voltage for setting a bias, is connected to the other input terminal via a feedback transistor connected as an emitter follower and an N junction, and A bias circuit characterized in that the voltage at the output end is further supplied via an emitter follower transistor to a current mirror circuit that serves as a current source for an electronic circuit.
JP16023382U 1982-10-25 1982-10-25 bias circuit Granted JPS5967019U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16023382U JPS5967019U (en) 1982-10-25 1982-10-25 bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16023382U JPS5967019U (en) 1982-10-25 1982-10-25 bias circuit

Publications (2)

Publication Number Publication Date
JPS5967019U true JPS5967019U (en) 1984-05-07
JPS631455Y2 JPS631455Y2 (en) 1988-01-14

Family

ID=30352485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16023382U Granted JPS5967019U (en) 1982-10-25 1982-10-25 bias circuit

Country Status (1)

Country Link
JP (1) JPS5967019U (en)

Also Published As

Publication number Publication date
JPS631455Y2 (en) 1988-01-14

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