JPS58141615U - gain control circuit - Google Patents
gain control circuitInfo
- Publication number
- JPS58141615U JPS58141615U JP3894182U JP3894182U JPS58141615U JP S58141615 U JPS58141615 U JP S58141615U JP 3894182 U JP3894182 U JP 3894182U JP 3894182 U JP3894182 U JP 3894182U JP S58141615 U JPS58141615 U JP S58141615U
- Authority
- JP
- Japan
- Prior art keywords
- gain control
- base
- pair
- transistors
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Receiver Circuits (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は現在考えられている利得制御回路の一例を示す
回路図、第２図はこの考案に係る利得制御回路の一実施
例を示す回路図である。FIG. 1 is a circuit diagram showing an example of a gain control circuit currently being considered, and FIG. 2 is a circuit diagram showing an embodiment of the gain control circuit according to this invention.
Claims (1)
ベースに入力信号が印加される一対のエミッタフォロワ
形トランジスタと、差動対を成すトランジスタの各ベー
スがそれぞれ抵抗を介して前記一対のエミッタフォロワ
トランジスタの各対応するエミッタに接続される差動増
幅回路と、前記差動対を成すトランジスタの各ベースと
利得制御電流源との間に挿入され利得制御電流のレベル
に応じて前記差動対を成すトランジスタのベースを流れ
る電流量を制御することにより差動増幅回路の利得を制
御するダイオードと、このダイオードによる利得制御動
作時に前記差動対を成すトランジスタのベース電圧を所
定の電圧にクランプするクランプ回路とを具備したこと
を特徴とする利得制御回路。A pair of emitter follower type transistors whose bases are respectively connected to a common power supply and an input signal is applied to at least one base, and each base of the transistors forming a differential pair is connected to each of the pair of emitter follower transistors through a resistor. a differential amplifier circuit connected to the corresponding emitter, and a differential amplifier circuit inserted between each base of the transistors forming the differential pair and a gain control current source, and controlling the transistors forming the differential pair according to the level of the gain control current. A diode that controls the gain of the differential amplifier circuit by controlling the amount of current flowing through the base, and a clamp circuit that clamps the base voltage of the transistors forming the differential pair to a predetermined voltage when the diode performs a gain control operation. A gain control circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3894182U JPS58141615U (en) | 1982-03-19 | 1982-03-19 | gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3894182U JPS58141615U (en) | 1982-03-19 | 1982-03-19 | gain control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58141615U true JPS58141615U (en) | 1983-09-24 |
Family
ID=30050251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3894182U Pending JPS58141615U (en) | 1982-03-19 | 1982-03-19 | gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58141615U (en) |
-
1982
- 1982-03-19 JP JP3894182U patent/JPS58141615U/en active Pending
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