JPS5933332U - amplifier circuit - Google Patents

amplifier circuit

Info

Publication number
JPS5933332U
JPS5933332U JP12840282U JP12840282U JPS5933332U JP S5933332 U JPS5933332 U JP S5933332U JP 12840282 U JP12840282 U JP 12840282U JP 12840282 U JP12840282 U JP 12840282U JP S5933332 U JPS5933332 U JP S5933332U
Authority
JP
Japan
Prior art keywords
amplifier circuit
transistor
output
turned
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12840282U
Other languages
Japanese (ja)
Other versions
JPH0221801Y2 (en
Inventor
和久 石黒
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP12840282U priority Critical patent/JPS5933332U/en
Publication of JPS5933332U publication Critical patent/JPS5933332U/en
Application granted granted Critical
Publication of JPH0221801Y2 publication Critical patent/JPH0221801Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を示す回路図、及び第2図
はその特性図である。 主な図番の説明、1・・・入力段差動増幅回路、4゜5
・・・ダイオード、6・・・正帰還型差動増幅回路、7
゜9.10・・・抵抗、17.18・・・駆動トランジ
スタ、20・・・制御トランジスタ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a characteristic diagram thereof. Explanation of main drawing numbers, 1...Input stage differential amplifier circuit, 4゜5
...Diode, 6...Positive feedback differential amplifier circuit, 7
゜9.10...Resistor, 17.18...Drive transistor, 20...Control transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力段差動増幅回路と、該入力段差動増幅回路の出力信
号によって駆動され、−・方のトランジスタのコレクタ
が他方のトランジスタのベースに接続される一対のトラ
ンジスタから成る正帰還型増幅回路と、該正帰還型増幅
回路の一方のトランジスタと電流ミラー関係に接続され
る第1ダイオードと、該第1グイオーデに流れる電流に
応じた出力電流を発生する第1出力回路と、前記正帰還
型増幅回路の他方のトランジスタと電流ミラー関係に接
続される第2タイオードと、該第2ダイオードに流れる
電流に応じた出力電流を発生する第2出力回路と、前記
第1及び第2出力回路の出力電流の差に応じてオンする
駆動トランジスタと、該駆動トランジスタの動作に応じ
てオンする制御トランジスタと、前記正帰還型増幅回路
の一方のトランジスタのエミッタに接続された第1抵抗
と、他方のトランジスタのエミッタに直列接続された第
2及び第3抵抗とから成り、入力段差動増幅回路に印加
される所定レベル以上の入力信号に応じて駆動トランジ
スタがオンし、制御トランジスタがオンして前記第3抵
抗を短絡し、前記第1乃至第3抵抗の値によって定まる
所定のヒステリシス特性を持つようにしたことを特徴と
する増幅回路。
an input stage differential amplifier circuit; a positive feedback amplifier circuit consisting of a pair of transistors driven by the output signal of the input stage differential amplifier circuit, and in which the collector of one transistor is connected to the base of the other transistor; a first diode connected in a current mirror relationship with one of the transistors of the positive feedback amplifier circuit; a first output circuit that generates an output current according to the current flowing through the first guide; and the positive feedback amplifier circuit. A second diode connected in a current mirror relationship with the other transistor, a second output circuit that generates an output current according to the current flowing through the second diode, and a difference in output current between the first and second output circuits. a drive transistor that is turned on according to the operation of the drive transistor, a control transistor that is turned on according to the operation of the drive transistor, a first resistor connected to the emitter of one transistor of the positive feedback amplifier circuit, and a first resistor connected to the emitter of the other transistor. Consisting of second and third resistors connected in series, the drive transistor is turned on in response to an input signal of a predetermined level or higher applied to the input stage differential amplifier circuit, and the control transistor is turned on to short-circuit the third resistor. An amplifier circuit characterized in that the amplifier circuit has a predetermined hysteresis characteristic determined by the values of the first to third resistors.
JP12840282U 1982-08-24 1982-08-24 amplifier circuit Granted JPS5933332U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12840282U JPS5933332U (en) 1982-08-24 1982-08-24 amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12840282U JPS5933332U (en) 1982-08-24 1982-08-24 amplifier circuit

Publications (2)

Publication Number Publication Date
JPS5933332U true JPS5933332U (en) 1984-03-01
JPH0221801Y2 JPH0221801Y2 (en) 1990-06-12

Family

ID=30291298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12840282U Granted JPS5933332U (en) 1982-08-24 1982-08-24 amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5933332U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6264284U (en) * 1985-10-08 1987-04-21
JPS63219223A (en) * 1986-10-17 1988-09-12 Sanyo Electric Co Ltd Drive circuit
JPH0366218A (en) * 1989-08-05 1991-03-20 Mitsubishi Electric Corp Voltage detection circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6264284U (en) * 1985-10-08 1987-04-21
JPH036218Y2 (en) * 1985-10-08 1991-02-18
JPS63219223A (en) * 1986-10-17 1988-09-12 Sanyo Electric Co Ltd Drive circuit
JPH0366218A (en) * 1989-08-05 1991-03-20 Mitsubishi Electric Corp Voltage detection circuit

Also Published As

Publication number Publication date
JPH0221801Y2 (en) 1990-06-12

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