JPH0366218A - Voltage detection circuit - Google Patents

Abstract

PURPOSE:To produce a hysteresis with high accuracy by arranging loads so that a current from a connecting point between output terminals of 1st and 2nd transistors(TRs) is shunted into two or more, and connecting at least one of said loads and a 2nd field effect TR in series. CONSTITUTION:The emitter of a 2nd npn TR 6 is connected to a 1st connecting point 9 via a 1st load 8 and the emitter of a 1st npn TR 4 is connected to the 1st connecting point 9 directly and respectively. A 2nd load 10 is connected to the 1st connecting point 9 and loads 67a, 67b are connected so that a current flowing to the 2nd load 10 is shunted. Moreover, the load 67a is connected directly and the load 67b is connected to a ground line 13 via a 2nd field effect TR 3n-MOST 68. Thus, the resistance of the load specifying a threshold voltage to cause a change in the level of an output voltage of a constant current source is varied with ON/OFF of a 2nd field effect TR 68 controlled with an output level of an inverter circuit 69.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage detection circuit for detecting fluctuations in voltage input to, for example, a microcomputer.

[Conventional technology]

FIG. 3 shows a conventional voltage detection circuit of this type, as disclosed in, for example, Japanese Unexamined Patent Publication No. 61-276413.

In FIG. 3, a first multi-collector pnp transistor (1) has a straw collector connected to a high potential point (3) connected to a power supply (2) of voltage +VCC, a second collector (1b) and a base connected to a high potential point (3) connected to a power supply (2) of voltage +VCC. 1npn) to the collector of transistor (4),
each connected. 2nd multi collector pnp
) The transistor (5) has its emitter connected to the high potential point (3), and its second collector (5b) and base connected to the collector of the second npn transistor (6). 1st
In this connection, the multi-collector l1) nll) transistor (1) and the second multi-collector pnp transistor (5) constitute a first current mirror circuit (30) and a second current mirror circuit (40), respectively. Both current mirror ratios are 1:1.

The emitter area ratio of the first npn) transistor (4) and the second npn) transistor (6) is 1:n, and both bases are connected to the signal input terminal (7). 2nd npn
) The emitter of the transistor (6) is connected to the first connection point (9) via the first load (8), and the emitter of the first npn) transistor (4) is directly connected to the first connection point (9). ing. Further, the second load α0) and the third load aD are connected in series at the second connection point (2), and the first connection point (9)
and the ground line 03), which is a low potential point. The first collector (1a) of the first multi-collector pnpl-transistor (1) is connected to the third connection point 00. The first of the second multi-collector pnp transistor (5)
The collector (5a) is connected to the collector of the 4th npn) transistor. Furthermore, the base and collector of the fourth npn transistor are connected. Third
The collector of the npn) transistor is connected to the third connection point αO, and the base of the third npnl-transistor α0 is connected to the base of the fourth npn) transistor Q51.
npn) Both emitters of the transistor are connected to the ground wire. The 3rd npn transistor 0 and the 4th npn transistor 0 constitute a third current ξ error circuit (50), and its current mirror ratio is 1:
It is 1. Further, a constant current source αD and a fifth npn transistor α are connected in series between the high potential point (3) and the ground line α, and the collector of the constant current source αD and the fifth npn transistor α is connected to the fourth Connected at connection point α.

The fourth connection point 0 is connected to the emitter of the third multi-collector pnp transistor (21) whose base is shared with the fifth npn transistor eω, and is further connected to the signal output terminal (2) via the collector of the fifth npn transistor r2φ.
2) is connected to. 3rd multi-collector I) n
p') first collector (21a) of transistor (21)
is connected to the second connection point (2) and the second collector (21b)
is connected to the common base of the 6th npnl transistor I2 and the third multi-collector 1)nl)) transistor (21), and the emitter of the 5th npnl transistor QO is connected to the ground line α.

Next, the operation will be explained.

By the input signal voltage VIN input to the signal input terminal (7), the first npn) run disk (4) and the second np
Collector current IC+ of each n transistor (6)
When and ICZ become equal, the input signal voltage is set as the threshold voltage. The above threshold voltage V, is the Boltzmann constant k, the electron charge q, and the absolute temperature T1 second npn.
) The voltage across the cap of transistor (6) is VBE
Z, the resistance of the first load (8) is R1, the resistance of the second load (00) is R2, and the resistance of the third load Qll is R3, it is given by the first equation.

(RI+2R2゜＞k T L”
+11 However, R2゜-Rz +R3 In the circuit configuration shown in Fig. 3, the first current mirror circuit (
30), since the current ratio of the second current ξ error circuit (40) and the third current ξ error circuit (50) is 1:1, the first current ξ error circuit (30)
■The current of the human power stage. , and the output stage current ■1 The input stage current rcz and the output stage current Iz of the second current ξ error circuit (40), and the input stage current I2 and the output stage current of the third current ξ error circuit (50). Current■. 3 is the same value. That is, it is shown by the second equation and the third equation.

Ic+-I+ -・-・(2)
IC! = 12 = IC3 (31 5th npn) The base current ■ of the transistor Ql is 1+ of the first current mirror circuit (30) and ■ of the third current mirror circuit (50). This is the difference from 3 and is expressed by the fourth equation.

1 B-1+ I C3−−−−−−−−−−
--When the input voltage of the 41 signal input terminal (7) is lower than the input voltage, the input voltage is applied to the bases of the first NPN transistor (4) and the second NPN transistor (6). First, the charge tends to flow to the emitter with the larger area, so tc+<Icg, and the second value voltage (2) changes to VSI given by the fifth equation.

VIN increases ■5. When it becomes equal to, rc+-
1C2, and from the second, third, and fourth equations, it becomes I 11-0. Therefore, as in the case of VIN<VS described above,
The transistor α of the fifth npn) is turned off, and the current flows to the emitter of the transistor (21). 3rd multi collector p
Since the current flows from the emitter to the base of the 6th npn) transistor (21) in the forward direction, the current is also given to the base of the 6th npn) transistor (2).
) The transistor (2) turns ON and the signal output terminal (22)
The potential of is a low potential level (hereinafter 'L'') which is almost the ground potential.
level).

At this time, the third multi-collector pnp transistor (2
1) Since the current rca flows from the first collector (21a) to the third load αD, the threshold Ic+> given by the first equation
It becomes Icz. This is the voltage from the base of the 1st npn) transistor (4) to the first connection point (9) and the 2nd npn)
The voltages from the base of the transistor (6) to the first connection point (9) are equal;
) and the second npn transistor (
Although there is a difference in the area to be built, there is usually not a large difference in resistance value from the base-external resistor in 6), so the 2nd np resistor to which the first load (8) is connected is
n) This is because the current flowing through the transistor (6) decreases. As a result, from the second, third, and fourth equations, In>O. Therefore, the fifth NPN transistor 0 is turned ON, the potential of the constant current source OD becomes almost the ground potential, and since sufficient current does not flow into the first collector (21a) of the third multi-collector PNP L transistor (21), it is turned OFF. Therefore, the sixth npnl-transistor (20) also becomes 0IIF, and the voltage V at the signal output terminal (22) becomes a high potential level (hereinafter referred to as ``1'' level).

At this time, since IC4 becomes sufficiently small, the threshold voltage changes from VSI given by the fifth equation to vs□, which is false given by the sixth equation. In other words, it becomes . This VS2 is approximately equal to the initial threshold value V3.

Now, next time when VIN starts to fall, the signal output terminal (
22) output V. is at the "H" level, so the threshold voltage is in the state of VS2 given by the sixth equation.

When VIN falls and becomes VIN=VSZ, ICI
"TCZ, so from the second and third equations, II = IC3, and from the fourth equation, ■, = 0. Therefore, the 5th npn
) transistor αO is turned OFF, and the current Io from the constant current source 07) flows from the emitter of the third multicurrent pnp transistor (21) to the base, and the base current also flows to the sixth npn transistor I2, which shares the base. Then, the 6th NPN transistor (A) turns on, and the potential of the signal output terminal (22) becomes ■.

is at the "L" level, which is approximately the ground potential. In this process, since Ica flows to the third load 0υ, the threshold voltage rises again to V31 shown by the fifth equation (as described above).

FIG. 4 is a diagram showing changes in the output voltage with respect to rises and falls in the input voltage of the voltage detection circuit provided with hysteresis by the conventional technique described above.

In FIG. 4, the solid arrow indicates the output signal voltage V when the input signal voltage V increases. [Problem to be solved by the invention] Since the conventional voltage detection circuit was configured as described above, in order to reduce the power consumption of the detection circuit, the current flowing through the multiple branches of the circuit became a minute current. When the current amplification factor h□ of the bipolar transistor used in the circuit decreases, the influence of the base current increases when current amplification is performed, and as a result, the output current of the current mirror circuit is not balanced. It becomes difficult and an off-cent occurs,
IB fluctuates even for the same input voltage, and the ON/OFF state of the fifth npn transistor is not constant, resulting in a decrease in the accuracy of voltage detection and the problem that hysteresis cannot be accurately produced in the output.

This invention was made in order to solve the above-mentioned problems, and is intended to detect changes in input signals in a low current consumption voltage detection circuit that has changed from a bipolar transistor configuration to an MO3 type field effect transistor (hereinafter referred to as MO3T) configuration. The object of the present invention is to obtain a voltage detection circuit that can produce accurate hysteresis in the output.

[Means to solve the problem]

The voltage detection circuit according to the present invention has an input terminal that independently receives the current of each of the manual stages of the first and second current mirror circuits connected to the first potential point, and a control terminal to which the same input signal is applied. , first and second transistors having output terminals connected to each other via a first load are provided, and the output stage of the third current short circuit receives the current of the output stage of the first current short circuit. The difference between the current and the current at the output stage of the second current mirror circuit is injected into the control terminal of the first field effect transistor to output a signal to the provided signal output terminal. The loads are arranged so that the current from the connection point of the output terminal of the transistor is divided into two or more, and at least one of the loads and the second field effect transistor are connected in series, and the output of the inverter circuit is used to The second field effect transistor is controlled.

[For production]

In the voltage detection circuit according to the present invention, the resistance value of the load that defines the threshold voltage for causing a change in the level of the output voltage of the constant current source is controlled by the output level of the inverter circuit. The threshold voltage is set so that it becomes low when the output becomes "L" level, and the threshold voltage becomes high when the output becomes "L" level. Therefore, when the input voltage increases, the threshold voltage becomes high, and when it decreases, the threshold voltage becomes low, so
Hysteresis occurs in the voltage at which the output level changes.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention. This embodiment uses the first current straw circuit (30
> and the second current ξ error circuit (40), for example, with a p-channel MO3T (hereinafter referred to as p-MO3T),
In addition, the third current mirror circuit (50) is, for example, an n-channel MO3T (hereinafter, n-channel MO3T is n-M
This is an example configured with O3T).

In FIG. 1, the input stage (31) of the first current mirror circuit (30) composed of the first p-MO3T (61) and the second p-MO5T (62) is connected to the power supply (2). The first potential point, here the high potential point (3), and the first transistor (1NPN) transistor (4)
is located between the collector and the collector. It is connected to the first motor.

In addition, the third p-MOS T (63) and the fourth p-MOS T (63)
The input stage (41) of the second current mirror circuit (40) composed of MOS T (64) also connects the high potential point (3) and the second current mirror circuit (40).
It is arranged between the collector of the second NPN transistor (6) and the collector of the second NPN transistor (6). Further, the output stage (42) of the second current accumulator circuit (40) is located at the high potential point (3).
and the drain of the second nM OST (66).

The area ratio of the first npn transistor (4) and the second npn transistor (6) is 1:n (in this example, n>1>, and the bases of both are connected to the signal input terminal (7). .

The emitter of the second npn) transistor (6) is connected to the first connection point (9) via the first load (8) and to the first
The emitters of the (npn) transistors (4) are directly connected to the first connection points (9), respectively. A second load 00) is connected to the first connection point (9), and a load (67a) and a load (67b) are connected so that the current flowing through the second load αψ is divided. Further load (67
a) directly and the load (67b) is the second field effect transistor, in this example the third n-MO3T (68).
It is connected to the ground wire α blade through. 1st n-MOS
The gates of T (65) and the second n-MOS T (66) are connected to each other, and the gates of the second n-MOS T (66) are connected to each other.
6) to form a third current ε error circuit (50), the current mirror ratio of which is 1.
:1. Further, the third current mirror circuit (50) is connected to the ground line α.

Further, the high potential point (3) is connected to a third connection point α via a constant current source αD, and one end of the third connection point a is connected to a signal output terminal (22) via an inverter circuit (69). It is connected to the. The other end of the third connection point α and the ground wire α
A first field effect transistor, in this example a fourth n-MOS T(TO), is connected between the transistor and the transistor. Further, the gate of the fourth n-MOS T (70) is connected to the second connection point (2). In addition, the above impark circuit (6
The output point of 9) is connected to the 3rd n-MO3T (6B).

Next, the operation will be explained.

First, considering that the output of the impark circuit (69) is at "L" level as an initial state, the 3rd n-MO3T (68) is OFF because no gate voltage is applied.
becomes. At this time, the threshold value Vsu is given by 2.

・−−−−−−−1−+7) However, R30=R2+R4 In the circuit configuration of FIG. 1, the first current mirror circuit (
30), the current mirror ratio of the second current mirror circuit (40) and the third current mirror circuit (50) is l:1.
Therefore, the current ICI at the input stage and the current I2 at the output stage of the first current mirror circuit (30) are 0, and the current IC2 at the input stage and the current I2 at the output stage of the second current mirror circuit (40).
, and the current I2 of the manual stage and the current LD3 of the output stage of the third current ξ error circuit (50) have the same value. That is, it is expressed by the second equation shown above and the eighth equation.

I CE = I z = 7113 ---
−−−−−−−−−−− (When the input voltage VIN of the R1 signal input terminal (7) is lower than V, as explained in the prior art, I., < Icz, and the second formula, Because of the relationship of the 8th equation, it is necessary that l<ID3, and the 4th n
- Charge is removed from the gate electrode of MO3T (70). Therefore, the gate voltage of the 4th n-MO3T (70) is not generated, so the 4th n-MO3T (70) does not generate a gate voltage.
0) is turned OFF, the output voltage of the constant current source becomes almost the power supply voltage Vcc, the "H" level is manually input to the inverter circuit (69), and "
L'' level is output. As a result, the third n-MOS T
(68) is turned OFF because no gate voltage is applied. Therefore, in this state, the threshold voltage remains at V9H.

When VIN increases and V becomes equal to VSll, Ic+=Icz, and the second equation, 8th 2 to 11"I
It becomes D3. At this time, the 4th n-MOST (70
) Since sufficient voltage is not applied to the gate electrode of
n-MO3T (70) becomes OFF, and the VIN<
As in the case of vsn, "L" level is output from the output point of the inverter circuit (69). Also at this time, the threshold voltage is VSll expressed by the seventh equation.

When VIN further increases and becomes higher than VSll, ICI>IC2, and from the second and eighth equations, t+>In3. Therefore, the excess current is the 4th nM O
The current flows into the capacitor formed by the gate electrode and source electrode of S T (70) as a storage current.

As a result, when the gate voltage of the 4th n-MOS T (70) reaches the operating voltage VTH, the 4th n-MOS T (To)
is turned on, the output potential of the constant current source αD becomes approximately the ground potential, the “L” level is input to the inverter circuit (69), and the “H” level is output from the output point of the inverter circuit (69). As a result, 3rd n-MO3T (6B)
is turned ON when a gate voltage is applied to it. The load at this time (
67b) is R5, and the ON resistance of the 3rd n-MO3T (68) is r, then the grounding wire α from the first connection point (9)
The resistance R3I up to turbidity is expressed by the ninth equation.

R31'''R2+R4〆I (Rs + r) -
−−−−−−+9+R3+ and initial value R shown in the 9th formula
There is a relationship with 3° as shown in Equation 10.

R3,<R3゜ -----------
−−−1−−−−−−−−00) Therefore, the output is “H”
The threshold voltage VSt after changing to the ``level'' is expressed by Equation 11.

R+ Q - - - - - - - - - - - - - When VIH falls while OD output V0 is at "H" level, the threshold voltage is VSL shown by equation 11. Yes, VIH-V3
It is maintained at this threshold until it reaches L, but VIN=VS
When it comes to L, it becomes Il-ID3, and the 4th n-MO
The gate voltage of ST(70) is no longer applied sufficiently,
The fourth n-MO5T (70) is turned OFF, and Vo becomes "L" level. Therefore, the third n-M OST
(68) is turned OFF, and the threshold voltage rises again to VSH given by the seventh equation.

FIG. 2 is a diagram showing changes in the output voltage \ with respect to rises and falls of the input voltage of a voltage detection circuit provided with a hysteresis function in one embodiment of the present invention described above.

In FIG. 2, solid arrows indicate changes in the output signal voltage vo when the input signal voltage VIN increases.
The dotted arrow indicates the change in Vo when vlN decreases.

Furthermore, in the above embodiment, the voltage detection circuit of a microcomputer was shown, but other microcomputer voltage detection circuits may be used.
A circuit including an O3T output circuit or the like may be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the output potential of the constant current source is switched to the first potential point potential or the second potential point potential by the first field effect transistor, and the signal output provided via the inverter circuit is In addition to outputting a signal to the terminal,
Loads are arranged so that the current from the connection point of the output terminals of the first and second transistors is divided into two or more, and at least one of the loads and the second field effect transistor are connected in series, and the inverter The second field effect transistor is controlled by the output of the circuit to change the resistance value of the load, and the threshold voltage for switching the output potential of the constant current source is changed, so the current flowing through the multiple branches of the circuit is Even when the current becomes a minute current, hysteresis can be accurately generated in the output signal with respect to the input signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the output-signal hysteresis of the voltage detection circuit according to an embodiment of the invention, and FIG. 3 is a diagram of a conventional voltage detection circuit. A circuit diagram of the circuit, FIG. 4, is a diagram showing hysteresis of an output signal of a conventional voltage detection circuit. In the figure, (3) is the first potential point, (4) is the first transistor, (6) is the second transistor, (8) is the first load, (131 is the second potential point, and α force is the constant current source. , (22) is a signal output terminal, (30) or (40) is a first current filter circuit, (40) or (30) is a second current mirror circuit, (50) is a third current mirror circuit, ( 67
a) and (67b) are loads, (68) is a field effect transistor, (69) is an inverter circuit, and (70) is a field effect transistor. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] First and second current mirror circuits connected to a first potential point; input terminals that independently receive the currents of the respective input stages of the first and second current mirror circuits, and the same input signal; first and second transistors having a control terminal to which is applied, and an output terminal connected to each other via a first load; a third current mirror circuit receiving the current of the first current mirror circuit as input; A signal output terminal that outputs a signal via an inverter circuit according to the output potential of a constant current source connected to one potential point, a current in the output stage of the third current mirror circuit, and an output of the second current mirror circuit. a first field-effect transistor that switches the output potential of the constant current source to a first potential point potential or a second potential point potential by injecting a difference between the current of the current source and the second potential point potential; A load arranged so that the current from the connection point of the output terminal of the transistor is divided into two or more, and a control terminal connected in series with at least one of the loads and controlled by the output of the inverter circuit. A voltage detection circuit comprising: a second field effect transistor.