JPH0366219A - Voltage detection circuit - Google Patents

Abstract

PURPOSE:To operate the circuit even when a current consumption of the voltage detection circuit is minute by controlling a bipolar transistor(TR) with the drain current of a field effect TR switching the output potential of a constant current source to the potential of a 1st potential level or the potential of a 2nd potential, and moving an excess charge to the 2nd level point. CONSTITUTION:A high potential point 3 is connected to a 3rd connecting point 17 via a constant current source 15 and one terminal of the 3rd connecting point 17 is connected to a signal output terminal 19 via an inverter circuit 18. The other terminal of the 3rd connecting point 17 is connected to the base of a bipolar TR pnp 67 and to the drain of a field effect TR 3n-MOST 68. Furthermore, excess charge stored between the gate and the source of the field effect TR controlling the output potential of the constant current source is moved to a low potential point via the bipolar TR 67. Thus, when an input signal voltage transits from a high threshold voltage to a low threshold voltage, the time required for a gate voltage decreased to the operating voltage is remarkably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage detection circuit for detecting fluctuations in voltage input to, for example, a microcomputer.

[Conventional technology]

FIG. 3 shows a conventional voltage detection circuit of this type, which is disclosed in, for example, Japanese Unexamined Patent Publication No. 61-27641.3.

In FIG. 3, the first multi-collector pnp transistor (1) is connected to a high potential point (3) connected to a power supply (2) of voltage +Vcc, with a second collector (1b) and a base connected to the 1npn) transistors (4), respectively. 2nd Margi collector pnl
)) The transistor (5) has its emitter at the high potential point (3),
The second collector (5b) and the base are respectively connected to the collector of the second npn transistor (6). In this connection, the first multi-collector pnp transistor (11) and the second multi-collector pnp transistor (5) are connected to the first current mirror circuit (30) and the second
A current mirror circuit (40) is configured, and both current mirror ratios are 1:l. The area ratio of the first npn) transistor (4) and the second npn) transistor (6) is 1:n (n>1), and the bases of both are connected to the signal input terminal (7). 2nd npnl-
The emitter of the transistor (6) is connected via the first load (8) to the first connection point (9) and to the first npn) transistor (
The emitters of 4) are each directly connected to the first connection point (9). A second load aυ is coupled between the first connection point (9) and the ground line αω, which is a low potential point. The first collector (la) of the first multi-collector pnp) transistor (11 is connected to the second connection point (2). The first collector (5a) of the second multi-collector pnp) transistor (5) is connected to the fourth npn ) Connected to the collector of transistor 0. Further, the base and collector of the fourth npn transistor 01 are connected. The collector of the 3rd npn transistor 0α is connected to the second connection point (2), and the base is connected to the base of the 4th npn transistor 01.
The emitters of the n-transistor 0ω are both connected to the ground line Q[11
It is connected to the. 4th npn) transistor α turbidity and 3rd
npn) transistor (141) also constitutes the third current mirror circuit (50), and its current mirror ratio is 1:
It is l. Further, a constant current source α and a fifth npn transistor α0 are connected in series between the high potential point (3) and the ground line 0ω, and the collector of the constant current source a9 and the fifth npn transistor 0ω is the third connection point. The emitter of the fifth npn transistor αO is connected to the ground wAQΦ. The third connection point αD is the inverter circuit α0
It is connected to the signal output terminal Ql via.

Next, the operation will be explained.

The input signal voltage VIN input to the signal input terminal (7) causes the first npn transistor (4) and the second npn transistor (4) to
n) Collector current ICI of each transistor (6)
When and ICZ become equal, the input signal voltage is set as the threshold voltage. The above threshold voltage V, is the Boltzmann constant k, the electron charge q, and the absolute temperature T1 second npn.
The voltage between base and terminal of transistor (6) is VBE2
, where the resistance of the first load (8) is R+ and the resistance of the second load αD is R2, it is given by the first equation.

R+Q (11 In the circuit configuration shown in Figure 3, the first current mirror circuit (
30), since the current mirror ratio of the second current mirror circuit (40) and the third current slurry circuit (50) is 1:1, the current rc+ of the input stage of the first current mirror circuit (30) and the output Stage current I.

Current rc2 at the input stage of the second current mirror circuit (40)
and the output stage current I2, and the third current accumulator circuit (
50), the input stage current I2 and the output stage current 1e2 have the same value. That is, it is shown by the second equation and the third equation.

Ic+=1+ (2) Ic
z = It = Ics (31st 5' n p n ) Base current I3 of transistor α
are ■ for the first current mirror circuit (30), and ■ for the third current mirror circuit (50). , and is expressed by the fourth equation.

11=II ICI +41
When the input voltage VIN of the signal input terminal (7) is lower than vs, the first npn) transistor (4) and the second npn
n) When an input voltage is applied to the base of the transistor (6), the charge tends to flow first to the one with the larger emitter area. ,<Icz, and from the second, third, and fourth equations, II<0. Therefore, the 5th npn) transistor (16) is turned off, and the output potential of the constant current source α9 becomes approximately +Vcc power supply potential, and the inverter circuit αω
A high potential level (hereinafter referred to as "H" level) is input to the signal output terminal α, and a low potential level (hereinafter referred to as "L" level) is output from the signal output terminal α.

When VIN is equal to ■3, ICI=IC2,
From the second, third, and fourth equations, IB=0. Therefore, the fifth npn) transistor Ql is turned off, and the Vl
As in the case of NkuVS, the "L" level is output from the signal output terminal α.

(2) When becomes higher than VSI, ICI>IC2. This means that the voltage from the base of the first npn transistor (4) to the first connection point (9) is equal to the voltage from the base of the second npn transistor (6) to the first connection point (9), and that 1npn) transistor (4) base resistor and 2nd npnl transistor (6)
Although the base-emitter resistance of
This is because the current flowing through the run disk (6) decreases. As a result, IB>O from the second, third, and fourth positions.

Therefore, the fifth npn transistor 0[O becomes ON,
The output potential of the constant current source 05) becomes the ground potential and is inputted to the inverter circuit αω at the “L” level, and the “H” level is output from the signal output terminal α.

[Problem to be solved by the invention]

Conventional voltage detection circuits are configured as described above, so when the current flowing through the circuit's multiple branches becomes a minute current, in order to reduce the power consumption of the detection circuit, the bipolar transistors used in the circuit are As the current amplification factor hFE decreases, the influence of the base current increases when performing current amplification, and as a result, it becomes difficult to balance the output current of the current mirror circuit, causing an offset, which causes the input voltage to be the same. Also, IB fluctuates, and the ON/OFF state of the fifth npn transistor is not constant, resulting in a decrease in voltage detection accuracy. In order to prevent this, it is necessary to change from the bipolar transistor configuration to an MO5 field effect transistor (hereinafter referred to as MO3T) configuration. However, when the transistor that controls the human power level to the inverter circuit is a Vibora transistor, it starts operating even with a minute base current, so the response is extremely good. However, when MO3T is used as the transistor,
When switching MO3T from ON to OFI', it is necessary to move the charge accumulated in the gate-source capacitance, but since the environment for moving charge is extremely poor under minute currents, this When the amount of accumulated charge to be moved is large and far apart, there is a problem in that the responsiveness deteriorates.

This invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a voltage detection circuit that has good responsiveness to changes in an output signal when an input signal changes, in a voltage detection circuit with low current consumption. It is said that

[Means to solve the problem]

The voltage detection circuit according to the present invention has an input terminal that independently receives the current of each input stage of the first and second current mirror circuits connected to the first potential point, and a control terminal to which the same input signal is applied. , first and second transistors having output terminals connected to each other via a first load are provided, and further a second transistor is provided between a connection point of the output terminals of the first # and second transistors and a second potential point. A load is provided to manually control the current in the output stage of the first current mirror circuit.The difference between the current in the output stage of the third current mirror circuit and the current in the output stage of the second current mirror circuit is connected to the control terminal of the field effect transistor. The output potential of the constant current source connected to the first potential point is switched to the first potential point potential or the second potential point, and a signal is output to the signal output terminal according to the output potential, and a signal is output to the signal output terminal according to the output potential. The bipolar transistor is controlled by the drain current of the field effect transistor, and surplus charge at the control terminal of the field effect transistor is moved to a second potential point via the bipolar transistor.

[For production]

Since the excess charge accumulated between the gate and the source is transferred to a low potential point via the hyperpolar transistor, the gate voltage of the field effect transistor does not rise above the emitter-collector saturation voltage of the bipolar transistor. Therefore, when the input signal voltage VIN transitions from a state higher than the threshold voltage V to a state lower, the time required for the gate voltage of the field effect transistor to drop to the operating voltage vTH of this field effect transistor is significantly shortened. be done.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention. This embodiment uses the first current controller circuit (30
) and the second current mirror circuit (40) are, for example, p-channel MO3T (hereinafter referred to as p-MO3T),
In addition, the third current mirror circuit (50〉) is, for example, an n-channel MO3T (hereinafter, n-channel MO3T is n −
This is an example configured with MOST.

In FIG. 1, the human power stage (31) of the first current and error circuit (30) composed of the 19th M03T (61) and the second p-MOS T (62) is connected to the power source (2).
The first potential point connected to, here the high potential point (3)
and the first transistor (1st npn) transistor (4
) is placed between the collector and the collector. The output stage (32) of the first current SLR circuit (30) is connected to the high potential point (3
) and the second connection point (2). The second connection point (2) is connected to the drain of the first n-MOST (65).

In addition, the third p-MO3T (63) and the fourth p-MOS
The second current mirror circuit (
The human power stage (41) of 40) is also arranged between the high potential point (3) and the collector of the second transistor (2nd NPN) transistor (6). Further, the output stage (42) of the second current short circuit (40) is arranged between the high potential point (3) and the drain of the second n-MOST (66).

The area ratio of the first npn transistor (4) and the second npn transistor (6) is 1:n (n>1 in this example), and the bases of both are connected to the signal input terminal (7). .

The emitter of said second npn l-transistor (6) is connected via a first load (8) to a first connection point (9), and the emitter of said first npn transistor (4) is connected directly to said first connection point (9). 1 connection point (9). The first connection point (9) and the grounding wire αω which is the second potential point
A second load αD is connected between the two. 1st n-MO
The gates of the 3T (65) and the second n-MOS T (66) are connected to each other, and the gates of the second n-MOS T (66) are connected to each other.
) is also connected to the drain of the third current mirror circuit (
50), and its current mirror ratio is 1:
It is 1. Further, the third current error circuit (50) is connected to the ground line αω.

Further, the high potential point (3) is connected to a third connection point αD via a constant current source a, and one end of the third connection point a'0 is connected to a signal output terminal 01 via an inverter circuit αω. ing. The other end of the third connection point Q7) is a bipolar transistor (in this embodiment, a flnp) transistor (6).
7), further connected to the base of the field effect transistor,
In this embodiment, it is connected to the drain of the third n-MOST (68). The third nM OST (
6B) has its source connected to the ground line Q[Il, and its gate connected to the second
It is connected to the connection point (2), and the collector is connected to the ground wire α.
0) connected to the above pnl)) transistor (67
) is also connected to the emitter of Note that the third n-MO3
The parasitic capacitance between the gate of T(68) and the ground line QOI (
69) indicates the parasitic capacitance between the gate and source.

Next, the operation will be explained.

The threshold voltage V is given by the first equation as explained in the conventional example.

In the circuit configuration of FIG. 1, the first current mirror circuit (
30), the current mirror ratio of the second current mirror circuit (40) and the third current mirror circuit (50) is 1:1.
Therefore, the current ICI of the input stage (31) of the first current mirror circuit (30), the current II of the output stage (32), and the current le2 of the input stage (41) of the second current mirror circuit (40) and the output The current I2 in the stage (42), and the current I2 in the input stage and the current ID3 in the output stage of the third current mirror circuit (50) have the same value. That is, it is expressed by the second equation shown above and the fifth equation.

I C2= I 2 = I D3 -----
−−−−−−−−−−−−− f5) Signal input terminal (7
) when the input voltage VIN;'l<Vs, ICI<IC!, as explained in the prior art. Then, the second
Because of the relationship of Equation 5 and Equation 5, it is necessary that l<ID3, and the charge is extracted from the gate electrode of the third n-MO3T (6B). Therefore, the third n-MO3T (6
Since the gate voltage of B) 6 is not generated, the 3rd n-MO3
T(68) is turned OFF, the drain voltage becomes "H" level, "H" level is input to the inverter circuit 00, and "L" level is output from the signal output terminal α0.

When VIN is equal to V3, ICI=IC! Then,
From the second and fifth equations, II = ID3. At this time, sufficient voltage is not applied to the gate electrode of the 3rd n'-MO3T (68), so the 3rd n'-MO3T (6B) is turned off.
As in the case of vlN-Vs, the "L" level is output from the signal output terminals α.

When Vo is higher than V3, as explained in the conventional technique, Ic+>Icz, and 2nd and 5th 2 to 11>ID3.
becomes. Therefore, the excess current is the third n-MO3T (68
) flows into the capacitor as a storage current formed by the gate electrode and source electrode. The third nM OS T (68
) is the value of parasitic capacitance (69) between the gate and source of CCS
Then, the gate voltage V is given by the sixth equation.

When V6 reaches the operating voltage VTI+ of the 3rd n-MO3T (6B), the 3rd n-MO3T (68) is turned on, the output potential of the constant current source α becomes the ground potential, and the “L” level appears at the inverter circuit α mark. The signal is input, and "H" horse mackerel rumor 1 is output from the signal output terminal.

This drain current (2) increases as the VG of the third n-MO5T (68) increases. At this time, In is pnp
) corresponds to the base current of the transistor (67), so a sufficient current I flows through the pnp transistor (67).
7) is ON, the excess charge on the gate electrode of the third n-MO3T (68) flows from the emitter electrode of the transistor (67) to the collector electrode of the transistor (67), so V6 becomes pn
The terminal-to-collection saturation voltage V of the p-transistor (67). It does not rise above (3□). i.e. I)np
) If there is no transistor (67), V6 is the power supply voltage V
cc, but when there is a pnp) transistor (67), VG is capped at VEC(satl).

FIG. 2 +8+ is a comparison diagram of the time course of V6 with and without the pnp transistor (67). In FIG. 2(a), the horizontal axis is time and the vertical axis is .

Also, in FIG. 2 (bl is pnp) the output signal voltage V depending on the presence or absence of the transistor (67). It is a comparative diagram of the time course of.

In FIG. 2 fb), the horizontal axis is time and the vertical axis is vo. Figure 2 (a), Figure 2 (bl is drawn with the origin of the time axis coincident. In Figure 2 fal, the above pnp) 3rd nMO without transistor (67)
3T (6B) (7) The gate voltage Vc is the dotted line (i.e. V
6□6□〉, and V when there is a pnp transistor (67) is shown by a solid line (ie, VGI curve). In Fig. 2, t is the time when the input voltage of the signal input terminal (7) becomes higher than the threshold voltage V, and t2 is the time when the input voltage of the signal input terminal (7) becomes lower than the threshold voltage V3. The time, tX, is the third n-M OS T (6
This is the time when the gate voltage V of 8) becomes Vtc (satl).

If we now set tl = 0, ■ from tl to t2.

The change in is the value of the parasitic capacitance (69) between the gate and source of the third n-MOS T (68) when CGS, 1 = 0, ■; when = 0, and t-CC, ■. = Vcc, the seventh formula % formula % (7) (However, α is a positive constant) ■The time Δt from G-0 to V, -VTI+ is p
np) It is expressed by the eighth equation regardless of the presence or absence of the transistor (67).

V cc Next, the gate voltage of the third n-MOS T (6B) is t-
The manner in which 〇 decreases from the initial value V6° is shown by Equation 9.

(However, β is a positive constant) Equation 9 is an equation in which t=0 at time t2 in FIG. 2 ia).

In the ninth equation, when VG −VGO begins to decrease, v
The time Δt2 until c=VtH is reached is given by Equation 10 (%) From Equation 10 (pnp) When there is a transistor (67),
The initial value is V G = V EC (in am, the above initial value V
Time Δt until ECcsat+ decreases to VTH
z+ is shown by the 11th equation.

TM VEC (If there is no smtl pnp transistor (67), the initial value is VG
-Vcc, the time Δtit required for the initial value Vcc to decrease to VTII is expressed by Equation 12.

cc Δt21 and Δt2 given by Equations 11 and 12
Since the magnitude relationship of □ is VTII<VECl, .<vCc, it is expressed by Equation 13.

By connecting the transistor (67) as in the present invention, the response becomes Δt2□Δtz+
only improved.

Furthermore, in the above embodiment, the voltage detection circuit of a microcomputer was shown, but other microcomputer voltage detection circuits may be used.
A circuit including an O3T output circuit or the like may be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the bipolar transistor is controlled by the drain current of the field effect transistor that switches the output potential of the constant current source to the first potential point potential or the second potential point potential, and the field effect transistor is controlled. Since the configuration is such that the excess charge at the terminal is moved to the second potential point via the bipolar transistor,
This has the effect that the voltage detection circuit can operate with good responsiveness even when the current consumption of the voltage detection circuit becomes very small.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention, Fig. 2 +a) is a diagram comparing the time course of gate voltage with and without a PNP transistor, and Fig.
) FIG. 3 is a circuit diagram of a voltage detection circuit according to the prior art. In the figure, (3) is the first potential point, (4) is the first transistor, (6) is the second transistor, (8) is the first load, Ql is the second potential point, 0υ is the second load, α9 is a constant current source, α is a signal output terminal, (30) or (40) is the first
(40) or (30) is a second current mirror circuit, (50) is a third current mirror circuit, (67) is a bipolar transistor, and (68) is a field effect transistor. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] First and second current mirror circuits connected to a first potential point; input terminals that independently receive the currents of the respective input stages of the first and second current mirror circuits, and the same input signal; first and second transistors having a control terminal to which is applied, and an output terminal connected to each other via a first load; a connection point between the output terminals of the first and second transistors and a second potential point; A second load provided in between, a third current mirror circuit which receives the current of the output stage of the first current mirror circuit, and a signal according to the output potential of a constant current source connected to the first potential point. The difference between the current at the output stage of the signal output terminal, the third current mirror circuit, and the output stage of the second current mirror circuit is injected into the control terminal, thereby increasing the output potential of the constant current source. a field effect transistor that switches the potential to a first potential point potential or a second potential point potential, and a bipolar transistor that is controlled by a drain current of the field effect transistor and moves surplus charge at a control terminal of the field effect transistor to the second potential point. A voltage detection circuit with a transistor.