JPH03104412A - Delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay circuit whose delay time is constant independently of temperature fluctuation by giving a bias voltage whose temperature characteristic is positive between a gate and a source of a 2nd MOS field effect transistor(TR). CONSTITUTION:A gate G2 of a 2nd MOS field effect TR M2 is subject to DC bias by a bias means comprising pnp bipolar TR pairs Q1, Q2 whose emitter areas differ, a 1st resistor R1, a 2nd resistor R2, a 3rd resistor R3 and an operational amplifier A1. Then a positive temperature characteristic is provided to a DC bias voltage VBIAS. It is possible to compensate the reduction in the drain current of the 2nd MOS field effect TR M2 due to the decrease in the mobility muN when the temperature rises by the increase of the gate-source voltage VGS(=VBIAS).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated delay circuit for digital signals, which charges a capacitor with a MOS field effect transistor current source or A circuit configuration is adopted in which a lamp voltage is generated by discharging accumulated charges, and a delay time is set using the time until this lamp voltage reaches a threshold value, and a MOS field effect is provided for charging and discharging accumulated charges. transistor gate,
Applying a bias voltage with positive temperature characteristics between sources (
This makes it possible to obtain a delay circuit that is more suitable for integration and whose delay time is less subject to temperature fluctuations.

BACKGROUND ART Digital circuits used in fields such as personal computers and digital measuring instruments require delay circuits that delay digital signals by a certain amount of time in order to adjust the timing between control signals. Conventionally, as this type of delay circuit, LC
High-precision ■C versions of delay elements and logic gate ICs for human output buffers are often used, but is it possible to reduce the size of the device? As delay circuits become thinner and cheaper, there is a strong desire to realize delay circuits that can be monolithically integrated.

This type of delay circuit, which is suitable for integration, generates a ramp voltage by charging or discharging a capacitor with a MOS field effect transistor current source, and uses the time it takes for this ramp voltage to reach a threshold value to calculate the delay time. A circuit system for setting is being considered.

Figure 10 shows a conventional delay circuit of this type. 1st
In Figure 0, M is the first MOS field effect transistor, M is the second Most field effect transistor, C is the capacitor, INV is the detection circuit, ■■■ is the DC bias voltage, VDD is the DC power supply voltage, and VIN is a digital human input signal which is a delayed signal, and VOLIT is a delayed signal given as a logic output. First MOS field effect transistor M. is composed of a P-channel element, whose gate Gl receives a digital input signal VIN, which is a delayed signal, and whose source is connected to a power line supplying a DC power supply voltage van.

The second MOS field effect transistor M2 is composed of an N-channel element, and its drain is commonly connected to the drain of the first MOS field effect transistor M1, and its source is connected to the ground power supply line. . A DC bias voltage VISIAS is applied to the gate G2.

The capacitor C is connected between a node a, which is a common connection point of the drains of the first and second MOS field effect transistors M, , M, and a ground, which is one of the power supply lines.

The detection circuit INV outputs a logic output corresponding to the amount of charge accumulated in the capacitor C as a delay signal V OUT. The detection circuit INV is composed of an inverter that converts the voltage level of node a into a binary signal, and the inverter outputs a low level when the voltage level of node a is higher than its threshold voltage VTH, and a high level when it is lower. Output.

FIG. 11 shows an example of operating waveforms of the delay circuit shown in FIG. 10. In the operational waveform example shown in FIG. 11, when the digital input signal VIN is at a low level, both the first MOS field effect transistor M and the second MOS field effect transistor M2 become active. At this time, node a
The voltage is the DC power supply voltage V. 0 is divided by the first MOS field effect transistor M1 and the second MOS field effect transistor M2, but the first MOS? The ratio (W/L) of the gate width W to the channel length L of the four-field effect transistor Ml is the same as that of the second MOS field effect transistor M2.
If it is sufficiently larger than that of the first MOS field effect transistor M1, the gate-source voltage of the first MOS field effect transistor M1 is equal to that of the second MOS field effect transistor M1.
Since it is larger than that of the S field effect transistor M2, the node a becomes a high level (approximately v op ), as shown in FIG. 11(b).

In this state, as shown in FIG. 11(a), when the digital input signal ■INIJ becomes high level when <t0, the first MOS field effect transistor M1 enters the cut-off state, so that the voltage accumulated in the capacitor C The charge is discharged through the second MOS field effect transistor M2.

The second MOS field effect transistor M2 has a gate G2
DC bias voltage VIIIAS is applied to , and its drain-source voltage VDS and gate-source voltage ■. In a saturation region where the relationship between SN (=V a + As) and threshold voltage v d s satisfies the following conditional expression VDS≧vasN-vtN, it operates as a fairly good constant current source. Therefore, when the digital input signal VIN becomes high level, the voltage at the node a starts to fall at a substantially constant slope, as shown in FIG. 11(b). This voltage at node a is monitored by a detection circuit INV composed of an inverter, and the voltage is set to the threshold voltage V of the inverter.
At time t1 when crossing TH, the inverter output V OUT is
As shown in FIG. 11(C), there is a transition from low level to high level.

In the above operation, the time required for the rising edge of the digital input signal VIN to be transmitted to the inverter output is the delay time Td. The delay time Td obtained by the conventional example shown in FIG. 10 is given by the following equation.

Td= (Voo-VTH) ・C/loN In the above equation, IDN is the second MOS field effect transistor M
2, which is approximately given by the following equation.

ION = (w.4/t.l.l) (μNCO/2
) (VGSN-VTN) “Here, vTN% LN
and wN are the threshold voltage, channel length and gate width of the second MOS field effect transistor M2, μ8
is the mobility of electrons, which are carriers of the second MOS field effect transistor M2, and C0 is the gate capacitance per unit area of the second MOS field effect transistor M2.

Problems to be Solved by the Invention However, in the conventional delay circuit described above, the carrier mobility μ decreases with temperature, so that the drain current of the second MOS field effect transistor M2 decreases. There is a drawback that N decreases with temperature, and as a result, the delay time increases as the temperature rises.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems and provide a delay circuit that is suitable for integration and whose delay time has little temperature fluctuation. Means for Solving the Problems> In order to solve the above problems, the present invention includes a first MOS field effect transistor, a second MOS field effect transistor, a capacitor, a detection circuit, and bias means. In the delay circuit, the first MOS field effect transistor has a gate to which a digital input signal as a delayed signal is guided, and a source connected to one of the power supply lines, and the second MOS field effect transistor The effect transistor has a drain commonly connected to the drain of the first MOS field effect transistor, and a source connected to the other power line, and the capacitor is connected to the drain common connection point of the MOS field effect transistor. The detection circuit is a circuit that outputs a logic output according to the amount of charge accumulated in the capacitor as a delay signal, and the bias means is connected to the second MOS electric field. It is characterized by a temperature characteristic that provides a positive bias voltage between the gate and source of the effect transistor.

<Function> Since the bias means is designed to apply a bias voltage having a positive temperature characteristic between the gate and source of the second MOS field effect transistor, the second MOS field effect transistor is It becomes possible to compensate for the decrease in the drain current of the MOS field effect transistor by increasing the gate-source voltage due to a bias voltage with positive temperature characteristics. Therefore, a delay circuit with a constant delay time can be obtained regardless of temperature fluctuations.

Embodiment> FIG. 1 shows an embodiment of the present invention. In the figure, the 10th
The same reference numerals as in the figures indicate identical components.

The feature of this embodiment is that the gate G2 of the second MOS field effect transistor M2 is a pair of pnp bipolar transistors with different emitter areas Q+%Q2, the first resistor R1, the second resistor
It is DC biased by a biasing means consisting of a resistor R2, a third resistor R3, and an operational amplifier A1. The operational amplifier A1 constituting the bias means has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) is connected to one emitter E1 of the bipolar transistor pair Ql, Q2, and the inverting input terminal (-) is connected to the other emitter E2 via a first resistor R1. Inverting input terminal (-)
is also connected to the non-inverting input terminal (◆
) are connected to the operational amplifiers A and A, respectively, via the third resistor R3.
is connected to the output terminal of And the operational amplifier A
．． The output terminal of the second MOS field effect transistor M
It is connected to the gate G2 of No. 2.

Operational amplifier AI amplifies the voltage difference between the non-inverting input terminal (+) and the inverting input terminal (-), and as a result biases the inverting input terminal (-) to the same potential as the non-inverting input terminal (+). do. Now, bipolar transistor pair Ql. The base-emitter voltage of Q2 is V IIEI, V B! 2, and the currents are I+ and Iz, the inverting input terminal (-) and the non-inverting input terminal (+
) are both l V ae+ l, so the output voltage of the operational amplifier A, that is, the gate bias voltage V! of the second MOS field effect transistor M2. IIAI1 is given by the following formula.

VIIIA! l ” VaEl ” 12R2=lVa
! +D (R2/Rl) (IVBEII-IVBE21
) = lVa! + 1” (R2/Rl) ・△Vae
'． '12=(lVael-lVazzl)/R
+ Difference in base-emitter voltage of bipolar transistor pair Ql, Q2 △VBE (=IVIIEII- IVBE21) However, VBt+l=(kT/Q)' An(1+/Is+)
VIIE2 1 = (kT/q) ・i n (12
/IS2) K: Boltzmann constant T: Absolute temperature q: Electron charge Is+: Saturation current of Q+ (proportional to emitter area S)
IS2: Saturation current of Q2 (proportional to emitter area 82)
It is given by the following equation. In addition, j! n represents a natural logarithm.

△VB! = (kT/q) ・1 n[(II/12
) (112/III)] Here, If/I2 −R2/R3 , Isz/Is+=S
Because there is a 2/S+ relationship, △VII! = (kT/q)・i n[(Rz/R,
) (S2/S1)] is obtained.

V BEI l has a negative temperature characteristic of about -2 (mV/t). On the other hand, (h/Rl)・△VaC is proportional to the absolute temperature, and is 0.085{Ri/R+)・in[(R2/Rs
)(S2/St)] (mV/t). Therefore, (R2/Rl) ・fL n [(R2/R3) (S
2/SL)] to an appropriate value, it is possible to give a positive temperature characteristic to the DC bias voltage V IIIAs, and the second MOS field effect transistor decreases in mobility μ9 when the temperature rises. The decrease in the drain current of M2 is determined by the gate-source voltage V. S(-V 61AS
) can be compensated for by increasing In combination with a MOS field effect transistor, (R2/R
l)' The practical value of fn[(Rz/R,)(S2/S+)] is 30 or more.

As shown in FIG. 2, the pnp bipolar transistors Ql and Q2 used in this example have a p+ diffusion layer as an emitter and an N well as a base, which are manufactured in the same process as the source/drain of a P channel MOS field effect transistor. By using the P-type substrate P-Sub as the collector, it can be easily manufactured using an N-well C-MOS process.

FIG. 3 shows a second embodiment of the present invention, and FIG. 4 shows an example of its operating waveforms. In this embodiment, in place of the pair of pnp bipolar transistors Q+ and Q2 in FIG. 1, npn bipolar transistors Q++ and Ql2 which are complementary thereto are used.

Correspondingly, the first MOS field effect transistor M
1 is composed of an N-channel element, and a digital human input signal (2), which is a delayed signal, is guided to its gate G, and its source is connected to a power supply line that is grounded.

Further, the second MOS field effect transistor M2 is composed of a P-channel element, and its drain is connected to the first MOS field effect transistor M2.
It is commonly connected to the drain of the field effect transistor M1, and its source is connected to a power supply line that supplies the DC power supply voltage DD. Gate G, is connected to npn bipolar transistor pair Q++, Ql2, resistor R. , Rl2,
DC bias is applied by bias means consisting of RI3 and operational amplifier AIO. In the operating waveform example of FIG. 4, the digital input signal VI
When N is at a high level, both the first MOS field effect transistor M and the second MOS field effect transistor M2 become active. At this time, the voltage at node b is the DC power supply voltage VDD, which is the voltage at the first MOS field effect transistor M.
It is a value obtained by dividing the voltage between l and the second MOS field effect transistor M2. ．． lm. :, the ratio of the gate width W to the channel length of the 741 MOS field effect transistor M (
W/L) is sufficiently large compared to that of the second MOS field effect transistor M2, then the first MOS field effect transistor M. The gate-source voltage of the second MO
Since it is larger than that of the S'F4 field effect transistor M2, the node b has a low level (
Approximately ov).

In this state, as shown in FIG. 4(a), when the digital human input signal VIN becomes low level at time t0, the first M
Since the OS field effect transistor M1 enters the cutoff state, the capacitor C is charged and sold by the second MOS field effect transistor M2. The second MOS field effect transistor M2 has a bias voltage VIIIA! on its gate G.
+ is applied and operates as a good constant current source.

Therefore, when the digital input signal vlN becomes low level, the voltage at node b rises at a substantially constant slope as shown in FIG. 4(b). This voltage at node b is monitored by a detection circuit INV monitored by the inverter, and at time t1 when the voltage crosses the threshold voltage VTH of the inverter, the inverter output VOUa becomes as shown in FIG. 4(C). Transition from high level to low level.

In the above operation, the time from 70:00 to 1:00 until the falling edge of the digital human input signal v1 is transmitted to the inverter output becomes the delay time Td. The delay time Td is given by the following equation.

Td- (VTHC)/IDP I of the above formula. P is the second MOS field effect transistor M2
The drain current is approximately given by the following equation.

Iop = (Wp/Lp) (μpCo/2) (V
Gsp-VTP)' where vTP. ．． Lp and Wp
are the threshold voltage, channel length and gate width of the 20th MOS field effect transistor M2, respectively, and μP is the second MOS field effect transistor M2.
The mobility of holes, which are carriers of the S field effect transistor M2, is the gate capacitance per unit area of the second MOS field effect transistor M2.

The operational amplifier AIO constituting the biasing means of this embodiment biases the inverting input terminal (-) to the same potential as the non-inverting input terminal (+), as in the first embodiment. The voltage of the non-inverting input terminal (+) is (V oo- V BEI 1
), so the output voltage vl! of the biasing means is lIA
s is given by the following formula.

VI11A8 ”VDO-VIIEII-I12Rl2
= t/no-V! lEtt-(R+z/Rz) (V
BEII-V! IE+2) = Voo-Vat r +
- (Rl 2/R port) ・ΔVa!゜．゜I+z=
(Vee++-VaE+z)/R++△VIE= (
kT/q) ・x I1[(RI2/RI3) (51
2/Sl1)] where Sl1 and SI2 are each Q
．． and the emitter area of Ql2.

At this time, the gate-source voltage VaS of the second MOS field effect transistor M2 is as follows.

VOS"Vl11AI -vao =- [Ver+++(R+z/Rz)・△Vac]
Therefore, (R+2/Rs+)・KL l1((Rl2/Rl3
) (S12/3+1)] to an appropriate value, as in the first embodiment, the drain current of the second MOS field effect transistor M2 due to the decrease in mobility μP when the temperature rises. The decrease in gate-source voltage IV
osl (=IVatAs VO (1+1 increase makes it possible to compensate.

npn bipolar transistor Q++ used in this example
and Q+2 are N-channel MOs as shown in FIG.
By using the n0 diffusion layer manufactured in the same process as the source/drain of the SIE field effect transistor as the emitter, the P well as the base, and the N type substrate as the collector, the P
It can be easily manufactured using a well C-MOS process.

The first embodiment is suitable for an N-well C-MOS process, and the second embodiment is suitable for a P-well C-MOS process.

FIG. 6 shows a third embodiment, and FIG. 7 shows an example of its operating waveforms. The feature of this embodiment is that the digital input signal VIN is branched into two paths, inverting and non-inverting, using inverters INVI and INV2, and in each path, a first circuit delays the rising edge and a second circuit delays the falling edge. 2 circuits, and attempts to reproduce the same pulse width as the input signal VIN by combining the outputs of the first circuit and the second circuit with a flip-flop FF that constitutes the detection circuit It is.

The first circuit includes a first MOS field effect transistor Ml
The gate G.1 of the first MOS field effect transistor M,1 is configured to include a second MOS field effect transistor M21 and a capacitor CI. A digital input signal VIN inverted by an inverter INVI is input to the inverter INVI.

The second circuit includes a first MOS field effect transistor M1
2. It is configured to include a second MOS field effect transistor M22 and a capacitor C2. The gate G,2 of the first MOS field effect transistor Ml2 receives a digital input signal V+H, which is obtained by further inverting the digital input signal VIN inverted by the inverter INV, and making it non-inverted as a result. Supplied.

The gates G21 and G22 of the second MOS field effect transistor M21%M22 are DC biased by a common biasing means. The bias means has the same structure as the second embodiment shown in FIG.

The detection circuit X consists of a flipflop FF and an inverter IN.
It is equipped with V3. flip flop FF
is an RS flip-flop composed of two NOR gates NoR and NOR2, and operates using the high level output of the first circuit as a set signal and the high level output of the second circuit as a reset signal.

The operation will be explained with reference to FIGS. 6 and 7.

M 7 As shown in Figure (a), the digital input signal v
1 is t. When it becomes high level, the inverter INVI
As shown in FIG. 7(b), the node C, which is the output end of the ? A priest's name appears.

This inverted signal is applied to the first MOS field effect transistor M
, I, the operation explained in FIGS. 3 and 4 causes the node d to be charged at to, which is the rising edge of the digital human power signal VIH, as shown in FIG. 7(C). A ramp waveform is obtained that starts with . Then, at time t1 when the ramp waveform crosses the threshold voltage vT}l of the flip-flop FF, the flip-flop FF is set, and as shown in FIG. 7(f), the inverter IN
A high level output v out is obtained from V3. The above-mentioned rise time delay from 70 o'clock to t1 o'clock is the delay time Tdt. It becomes n.

On the other hand, as shown in FIG. 7(a), when the digital input signal VIN falls to a low level at time t, which is delayed by the pulse width of the digital input signal VIN from time t0, as shown in FIG. 7(d). As shown in FIG. 2, a non-inverted signal whose state also changes to the low level appears at the node e, which is the output end of the inverter INV2. This non-inverted signal is the first M
Given to the gate GI2 of the OS field effect transistor M,■? Therefore, as shown in FIG. 7(e), the falling edge of the digital input signal VTN is applied to the node f.
A ramp waveform is obtained that starts charging at time t2. Then, at the time t when the ramp waveform crosses the threshold voltage VT of the flip-flop FF, the flip-flop FF is reset, and as a result, the output V of the inverter I N V s. uT becomes low level as shown in FIG. 7(f). The falling time delay from time t2 to time t3 becomes delay time TdHL.

Therefore, the second MOS field effect transistor M2l%M
By appropriately selecting the size (M/L) of 22 and the capacitance values of capacitors C1 and C2, the digital human input signal V
An output signal v out with the same pulse width as IN can be obtained. Furthermore, if necessary, the rising and falling delay times TdLo and TdHL can be set independently.

FIG. 8 shows a fourth embodiment, and FIG. 9 shows an example of its operating waveforms. This embodiment, like the third embodiment shown in FIG. and a second circuit that delays the rising edge,
By combining the outputs of the first circuit and the second circuit with the flip-flop FF that constitutes the detection circuit X, it is attempted to reproduce the same pulse width as the human input signal VIN. The feature of this embodiment is that the bias means has the same structure as that of the first embodiment shown in FIG. 1, and the flip-flop FF is composed of a NAND gate.

The first circuit includes a first MOS field effect transistor M.
, a second MOS field effect transistor M2, and a capacitor C1, and the first MOS field effect transistor M. A digital input signal V is input to the gate Gll of
IN is input.

The second circuit includes a first MOS field effect transistor MI
2. The circuit includes a second MOS field effect transistor M22 and a capacitor C2, and an inverter IN is connected to the gate Gl2 of the first MOS field effect transistor M12.
An inverted digital human input signal VIN is supplied at VI.

Gates G21 . of the second MOS field effect transistors M21, M22. G22 is DC biased by a common biasing means. The bias means has the same structure as the first embodiment shown in FIG.

The detection circuit X includes a flip-flop FF and an inverter IN.
V3. flip flop F
F is two NAND gates NAND, and NAND
This is an RS flip-flop consisting of 2 circuits, which operates using the low level output of the first circuit as a set signal and the low level output of the second circuit as a reset signal.

The operation will be explained with reference to FIGS. 8 and 9. As shown in FIG. 9(a), the digital input signal VIN is t0
When the digital input signal reaches a high level,
First MOS field effect transistor M. Gate G. Therefore, by the operation explained in FIGS. 1 and 11, as shown in FIG. 9(c), a ramp waveform is created at the node d that starts discharging at the rising edge of the digital input signal VIN. is obtained. Then, the ramp waveform is the threshold voltage VT of the flip-flop FF}
The flip-flop FF is set at 11 o'clock when the inverter INVs crosses 1, and as shown in FIG. 7(e), a high-level output V is generated from the inverter INVs. LIT is obtained. t mentioned above.

The rise time delay from 1,000 to 1,000 is the delay time Td
It becomes LH.

On the other hand, as shown in FIG. 9(a), when the digital input signal VIN rises to a low level at time t2, which is delayed by the pulse width of the digital input signal VIN from time t0, the signal at node e, which is the output end of the inverter INVI, On the other hand, as shown in FIG. 9(c), an inverted signal whose state changes to high level appears. Since this inverted signal is applied to the gate G12 of the first MOS field effect transistor M,2, the falling edge of the digital human input signal VIH, t2, is applied to the node f, as shown in FIG. 9(d). A ramp waveform is obtained that starts discharging at certain times. Then, at time t3 when the ramp waveform crosses the threshold voltage of the flip-flop FF, the flip-flop FF is reset, and as a result, as shown in FIG. 9(f), the inverter INV3
to low level output V. UT is obtained. The fall time delay from time t2 to time t is the delay time Td}lL
becomes.

Therefore, also in this embodiment, the size (W/L
), by appropriately selecting the capacitance values of the capacitors CI and C2, it is possible to obtain the output signal VOLIT with the same pulse width as the digital input signal VIN. In addition, if necessary, the delay time Td of rising and falling
L. and Td}I, can also be set independently.

A plurality of delay circuits of the embodiment shown in FIG. 6 and the embodiment shown in FIG.
By setting it as the next stage digital input signal VIN,
Output signal V of each stage. A tapped delay circuit that uses UT as a tap output can be constructed.

When constructing a tapped delay circuit using the delay circuit shown in FIG.
Output signal of NOR (input signal of inverter INV)
is the digital input signal VIN of the next stage, and the inverter I
NV, the output signal is transferred to the second MOS field effect transistor M
The output signal of the inverter INV2 is applied to the gate Gl2 of the first field effect transistor M, and the gate Gl2 of the first field effect transistor M. It is effective to prevent the additional delay time caused by the load capacitance of the tap output (inverter Nv3 output) from being transmitted to the next stage.

Similarly, when constructing a tapped delay circuit using the delay circuit shown in FIG.
input signal) as the next stage digital human input signal VIN,
This input signal VIN is applied to the gate Gl2 of the second MOS field effect transistor Mll, and the output signal of the inverter INVI is applied to the gate Gll of the first field effect transistor M.
If the configuration is such that the tap outputs (inverters INV and ?) are respectively guided, it is effective to prevent the additional delay time caused by the load capacitance of the tap outputs (inverters INV and INV) from being transmitted to the next stage.

When configuring such a tapped delay circuit, it is not necessary to provide bias means for each stage.

Multiple stages of second MOS field effect transistors M2,,M
, ■ can be biased in common by one biasing means to reduce the occupied area and power consumption.

In the above embodiment, in order to obtain a gate-source voltage with positive temperature characteristics, a p
Although the case has been described in which the base-emitter voltage difference ΔVBE of an np or npn bipolar transistor is used, similar effects can be obtained by replacing these with pn or np junction diodes. The circuit configuration in this case can be inferred from the above-mentioned embodiments.

That is, the anodes of the diode pair are connected in common and led to the power supply line. The non-inverting input terminal of the operational amplifier leads to the cathode of one of the diode pairs and is connected to the output terminal of the operational amplifier via a third resistor. The inverting input terminal is the first
It is led to the other cathode of the diode pair through a resistor, and is connected to the output terminal of the operational amplifier through a second resistor. Then, the output terminal of the operational amplifier is connected to the second MOS
This is a circuit configuration that leads to the gate of a field effect transistor.

In this case as well, the area of the cathode connected to the first resistor of the diode pair is 32, the area of the other cathode is S, the value of the first resistor is R1, and the value of the second resistor is R, and the value of the third resistor is R, (R2/Rl) -x n ((R2/R3) (S2
/51)]≧30.

Effects of the Invention> As described above, the delay circuit according to the present invention has the first M
A delay circuit comprising an OS field effect transistor, a second MOS field effect transistor, a capacitor, a detection circuit, and biasing means, the first MOS field effect transistor having a digital signal at its gate that is a delayed signal. The input signal is guided, and the second MOS field effect transistor has a source connected to the first power supply line, a drain commonly connected to the drain of the first MOS field effect transistor, and a source connected to the first power supply line. The capacitor is connected between the drain common connection point of the MOS field effect transistor and the power supply line, and the detection circuit delays the logic output according to the amount of charge accumulated in the capacitor. It is a circuit that outputs a signal, and the bias means is designed to apply a bias voltage with positive temperature characteristics between the gate and source of the second MOS field effect transistor, so it is suitable for integration and has a short delay time. It is possible to provide a delay circuit with less temperature fluctuation.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram of a delay circuit according to the present invention, FIG. 2 is a diagram showing the configuration of a pair of pie boiler transistors that prevent biasing means, and FIG. 3 is another implementation of the delay circuit according to the present invention. A circuit diagram showing an example, FIG. 4 is a diagram showing an example of its operating waveform,
FIG. 5 is a diagram showing the configuration of a bipolar transistor pair that configures the bias means, FIG. 6 is a circuit diagram of yet another embodiment of the delay circuit according to the present invention, and FIG. 7 is an example of its operating waveform. 8 is a circuit diagram of yet another embodiment of the delay circuit according to the present invention, FIG. 9 is a diagram showing an example of its operating waveforms, FIG. 10 is a circuit diagram of a conventional delay circuit, and FIG. It is a figure which shows the example of an operation|movement waveform. Ml-MII% M+2...First MOS field effect transistor M2.M2.
%M22...Second MOS field effect transistor INV...
Detection circuit X...Detection circuit Ql. Q2...
Bipolar transistor pair Qt+xQt2...Bipolar transistor pair R1, Rl+...First resistor R2, Rl2...Second resistor R1, Rl3...Third resistor Figure 2 Figure 3 Figure 4 Figure 7 Figure 10 Figure 1l Figure

Claims (5)

[Claims] (1) A first MOS field effect transistor and a second M
A delay circuit including an OS field effect transistor, a capacitor, a detection circuit, and a biasing means, wherein the first MOS field effect transistor has a gate to which a digital input signal as a delayed signal is led, and a source to which a digital input signal is guided. is connected to one of the power supply lines, and the drain of the second MOS field effect transistor is commonly connected to the drain of the first MOS field effect transistor, and the source is connected to the other power supply line. The capacitor is connected between a drain common connection point of the MOS field effect transistor and the power supply line, and the detection circuit outputs a logic output according to the amount of charge accumulated in the capacitor as a delayed signal. A delay circuit that outputs an output, wherein the bias means applies a bias voltage having a positive temperature characteristic between the gate and source of the second MOS field effect transistor. (2) The bias means includes a bipolar transistor pair, an operational amplifier, a first resistor, a second resistor, and a third resistor.
The bipolar transistor pair has a collector and a base connected in common and is led to a power supply line, and the operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is guided to one emitter of the bipolar transistor pair and is connected to the output terminal via a third resistor, and the inverting input terminal is connected to the first resistor. and is guided to the other emitter of the bipolar transistor pair through the
2. The delay circuit according to claim 1, wherein the delay circuit is connected to the output terminal via a second resistor, and the output terminal is led to the gate of the second MOS field effect transistor. (3) The bias means includes a diode pair, an operational amplifier, a first resistor, a second resistor, and a third resistor, and the diode pairs have anodes connected in common to a power supply line. The operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal, and the non-inverting input terminal is led to the cathode of one of the diode pairs, and the operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. 3, the inverting input terminal is connected to the other cathode of the diode pair via the first resistor, and the inverting input terminal is connected to the second cathode of the diode pair through the first resistor.
2. The delay circuit according to claim 1, wherein the delay circuit is connected to the output terminal via a resistor, and the output terminal is led to the gate of the second MOS field effect transistor. (4) Of the bipolar transistor pair, the area of the emitter connected to the first resistor is S_2, the area of the other emitter is S_1, the value of the first resistor is R_1, the value of the second resistor is R_2, When the value of the third resistor is R_3, (R_2/R_1)・ln[(R_2/R_3)(S_
2/S_1)]≧30. The delay circuit according to claim 2, wherein the delay circuit satisfies the following. (5) Of the diode pair, the area of the cathode connected to the first resistor is S_2, the area of the other cathode is S_1, the value of the first resistor is R_1, and the value of the second resistor is R
_2, when the value of the third resistor is R_3, (R_2/R_1)・ln[(R_2/R_3)(S_
4. The delay circuit according to claim 3, wherein the delay circuit satisfies the following: 2/S_1)]≧30.