JPH04304017A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption without simultaneous turning-on of plural analog switches by setting a ratio of the width of P-channel and N- channel transistors(TRs) to the length of a gate to a different value from 1st and 2nd CMOS inverters. CONSTITUTION:Let a ratio of the ratio of the width of a P-channel TR3 to the length of the gate to the ratio of the width of an N-channel TR4 to the length of a gate be A, then let a ratio of the ratio of the width of a P-channel TR8 to the length of the gate to the ratio of the width of an N-channel TR9 to the length of the gate be B. The ratios A, B are set different to form the threshold level of CMOS inverters 5, 10 different. Thus, when an input waveform is applied to an input terminal 1, the simultaneous turning-on of a 1st analog switch 12 and a 2nd analog switch 13 is avoided, and the circuit is operated with a prescribed time difference. Thus, the power consumption is reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to an analog switch driver.

0002

[Prior Art] Inverter section 1 of a conventional semiconductor integrated circuit
02 is a first P-channel transistor 42 and gate whose gate is connected to the input terminal 39, whose drain is connected to the first output terminal 45, and whose source is connected to the high potential power supply line 40, as shown in FIG. a first CMOS inverter 44 with a first N-channel transistor 43 connected to the input terminal 39, a drain connected to the first output terminal 45, and a source connected to the low potential power supply line 41; A second P-channel transistor 48 has the same transistor size as the first P-channel transistor 42 connected to the terminal 39, its drain is connected to the second output terminal 51, and its source is connected to the high potential power supply line 40, and its gate is connected to the input terminal. 39, a drain connected to the second output terminal 51, and a source connected to the low potential power supply line 41.
It has a second CMOS inverter 50 with a channel transistor 49. Also, the analog switch section 202
is a third inverter 46 whose input terminal is connected to the first output terminal 45 and whose output terminal is input to the second analog switch 47.
It has an analog switch 47 driven by the output of , and a second analog switch 52 driven by the voltage vd of the second output terminal 51.

Generally, the characteristics of a P-channel transistor and an N-channel transistor can be expressed by the following equations (1) and (2), respectively.

0004

[0005] When the low potential power supply line 41 is set to GND, V
DD is the potential of the high potential power line 40, VIN is the gate voltage,
VTP and VTN are P channel transistors and N
This is the threshold of the channel transistor. WP and LP are the transistor width and gate length of the P-channel transistor,
WN and LN are the transistor width and gate length of the N-channel transistor. βP and βN are constants of the P-channel transistor and N-channel transistor determined by the transistor manufacturing process.

The threshold voltage of the first inverter 44 and the second inverter 50 is (VDD/2), and |VTP
If there is a relationship of |=|VTN|, 2βP=βN, then (WP/LP) of the first P-channel transistor 42 and the second P-channel transistor 48 and the N-channel transistor 49
The relationship between (WN/LN) and (WN/LN) is as shown in the following equation (3). Also in the layout, the first inverter 44 and the second inverter 50 are laid out so as to satisfy this equation (3).

(WP/LP)=20(WN/LN) (3) The first analog switch 47 is an analog switch that is turned on when the output of the third inverter 46 is at a high level. The second analog switch 52 is an analog switch that is turned on when the second output terminal 51 is at a high level.

When the input waveform shown in FIG. 5 is input to the input terminal 39, waveforms at the output point PC of the third inverter 46 and at the Pd point of the second output terminal 51 are obtained. A time occurs at which the first analog switch 47 and the second analog switch 52 are simultaneously turned on at time t1.

[0009]

[Problems to be Solved by the Invention] This conventional semiconductor integrated circuit has a first CMOS inverter and a second CMOS inverter.
Since the threshold voltages of the inverters are the same, there is a problem in that when an input waveform is applied to the input terminal, the first analog switch and the second analog switch are turned on at the same time.

0010

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a first P-channel transistor whose gate is connected to an input terminal and whose source is connected to a high potential power supply line; a first C-channel transistor having a first N-channel transistor connected to a low potential power supply line and having a drain connected to the drain of the first P-channel transistor;
a MOS inverter; a second P-channel transistor having a gate connected to the input terminal, a source connected to the high potential power line; a second P-channel transistor having a gate connected to the input terminal, a source connected to the low potential power line, and a drain connected to the a second CMOS inverter having a second N-channel transistor connected to a drain of the second P-channel transistor; Let A be the ratio of the transistor width to the gate length of the first N-channel transistor, and let A be the ratio of the transistor width to the gate length of the second P-channel transistor and the transistor width to the gate length of the second N-channel transistor. If the ratio with the ratio of
The threshold values of the OS inverter and the second CMOS inverter are configured differently.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. The semiconductor integrated circuit includes a first P-channel transistor 3 whose gate is connected to a first input terminal 1, whose source is connected to a high potential power supply 2, and whose drain is connected to the input terminal of an inverter 6, and whose gate is connected to a first input terminal 1. 1, a first N-channel transistor 4 having a source connected to GND, and a drain connected to the input terminal of the inverter 6, and a first CMOS inverter 5 having a gate connected to the first input terminal 1 and a source connected to a second P-channel transistor 8 whose gate is connected to the high potential power supply 2 and whose drain is connected to the first output terminal 7; whose gate is connected to the input terminal 1, whose source is connected to GND and whose drain is connected to the first output terminal 7; The inverter section 100 includes a second CMOS inverter 10 including a second N-channel transistor 9 connected to the inverter section 100 .

[0012] Also, a first analog terminal is connected at one end to the second output terminal 11 and at the other end to the upper electrode of the capacitor 14.
switch 12 and a second analog line connected at one end to the upper electrode of capacitor 14 and at the other end to analog GND line 18.
A switch 13 has one end connected to the third output terminal 15 and the other end connected to the lower electrode of the capacitor 14 to provide a third analog signal.
An analog switch section 2 having a switch 16 and a fourth analog switch 17 having one end connected to the lower electrode of the capacitor 14 and the other end connected to the analog GND line 18.
00.

First analog switch 12 and fourth analog switch 17 of analog switch section 200
is an analog switch that is turned on when the output voltage of the inverter 6 is at a high level. Also, the second analog
The switch 13 and the third analog switch 16 are analog switches that are turned on when the first output terminal 7 is at a high level.

Next, the operation of the circuit will be explained using specific numerical examples. The constant βP of the transistor is multiplied by 10 to the 6th power (
16A/V・V), βN is 2βP, N channel and P
It is assumed that the threshold voltage of the channel transistor is 0.8V and the voltage of the high potential power supply line 2 is 5V. Here, in order to set the threshold voltage of the first CMOS inverter 5 constituted by the first P-channel transistor 3 and the first N-channel transistor 4 to 3.5V, the above-mentioned formula (1) is used. (WP/LP) according to formula (2)
It is only necessary that =30.0·(WN/LN) hold. Therefore, if LN=LP=2μm, WN=10μm, WP=3
00 μm. Similarly, in order to set the threshold voltage of the second CMOS inverter 10 constituted by the second P-channel transistor 8 and the second N-channel transistor 9 to 1.5V, 7.4·(
It is sufficient if WP/LP)=(WW/LN) holds true. Now, if LN=LP=2μm, WP=10μm, WN
=74 μm.

The threshold voltage of the inverter 6 is 2
．． When the voltage is 5V, the rise and fall times in Figure 2 are 10n.
When input waveform v1 of sec is added to input terminal 1, inverter 6
The output waveform v6 of the output terminal 7 and the waveform v7 of the output terminal 7 are obtained, and the on-time of the first analog switch 12 and the fourth analog switch 17 and the second analog switch 13 are
There can be a period of 4 nsec between the turn-on time of the third analog switch 16 and the turn-on time of the third analog switch 16. As a result, the charges accumulated in the cell 14 are held without leaking.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The inverter section 101 includes a first P-channel transistor whose gate is connected to the first input terminal 19, whose source is connected to the high potential power supply line 20, and whose drain is connected to the first output terminal 28, and whose gate is connected to the first input terminal 28. Connect to terminal 19 and connect the source to G.
A first CMOS inverter 27 consisting of a first N-channel transistor 26 connected to ND and whose drain is connected to the first output terminal 28, and whose gate is connected to the first input terminal 19 and whose source is connected to a high potential. A second P-channel transistor 21 is connected to the power supply line 20 and its drain is connected to the input of the first inverter 24, and its gate is connected to the first input terminal 1.
9 and a second N-channel transistor 22 having its source connected to GND and its drain connected to the input of the first inverter 24.
3.

The analog switch section 201 has one end connected to the second input terminal 29 and the other end connected to the second inverter 31.
a first analog switch 30 connected to the input of the second inverter 31; a second analog switch 32 having one end connected to the input of the second inverter 31 and the other end connected to the output of the third inverter 33; A third analog switch 3 connected to the output of the second inverter 31 and the input of the third inverter 33 and the other end connected to the input of the fourth inverter 35
4, and a fourth analog switch 36 having one end connected to the input of the fourth inverter 35 and the other end connected to the output of the fifth inverter 37.

The second output terminal 38 is connected to the fourth inverter 3
5 and the input of the fifth inverter 37. The first analog switch 30 and the fourth analog switch
The switch 36 is an analog switch that is turned on when the first output terminal 28 is at a high level. The second analog switch 32 and the third analog switch 34 are analog switches that are turned on when the output of the first inverter 24 is at a high level.

In order to set the threshold voltage of the first inverter circuit 27 to 1.5V, the transistor size of the first P-channel transistor 25 is such that the gate length is 2 μm.
, the transistor width is 10 μm, and the transistor size of the first N-channel transistor 26 is such that the gate length is 2 μm and the transistor width is 74 μm. In order to set the threshold voltage of the second inverter circuit 23 to 3.5V, the transistor size of the second P-channel transistor 21 is such that the gate length is 2 μm and the transistor width is 300 μm.
The transistor size of the second N-channel transistor 22 is 2 μm in gate length and 10 μm in transistor width.

Input signal v input to first input terminal 19
19 from a low level to a high level in 10 nsec, the inverter voltage V28 of the first output terminal 28 falls, and then it takes 4 nsec until the output of the first inverter 24 rises, as in the waveform diagram of FIG. There is time for or,
When the signal v19 input to the first input terminal 19 falls from high level to low level in 10 nsec, the first output terminal voltage V28 rises, and then the first inverter 2
There is a time of 4 nsec until the output of No. 4 falls.

[0021] Therefore, the first analog switch 30 and the second analog switch 32 are not turned on at the same time. Also, a third analog switch 34 and a fourth analog switch 34
Switch 36 is also not turned on at the same time. Therefore, the third inverter 33 and the second input terminal 29 are not short-circuited, and the second inverter 31 and the fifth inverter 3
7 is not shorted. Therefore, the power consumption of the circuit can be reduced.

[0022]

[Effects of the Invention] As explained above, the present invention provides the first C.
In the P-channel transistor and N-channel transistor constituting the MOS inverter, and the P-channel transistor and N-channel transistor constituting the second CMOS inverter, the transistor width and gate length ratios of the P-channel and N-channel transistors are set as the first and second ratios. CM of
The first CM is set to a different value than the OS inverter.
The threshold voltage of the OS inverter and the threshold voltage of the second CMOS inverter are different, which has the effect that a plurality of analog switches are not turned on at the same time and power consumption is reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the invention.

FIG. 4 is a circuit diagram of an example of a conventional semiconductor integrated circuit.

FIG. 5 is a signal waveform diagram of each part for explaining the operation of the circuit of FIG. 4;

[Explanation of symbols]

1 Input terminals 2, 20 High potential power supply lines 3, 25 First P channel transistors 4, 2
6 First N-channel transistor 5, 27
First CMOS inverter 6, 24 Inverter 7, 28 First output terminal 8, 21 Second P-channel transistor 9, 2
2 Second N-channel transistor 10, 23
Second CMOS inverter 11, 38 Second output terminal 12, 30 First analog switch 13, 3
2 Second analog switch 14 Capacitor 15 Third output terminal 16, 34 Third output terminal 17, 36 Fourth output terminal 18 Analog GND line 100, 101 Inverter section

Claims (1)

[Claims] 1. A first P-channel transistor having a gate connected to an input terminal and a source connected to a high potential power supply line, a gate connected to the input terminal, a source connected to a low potential power supply line, and a drain connected to the first P-channel transistor. a first CMOS inverter having a first N-channel transistor connected to the drain of the P-channel transistor; a second P-channel transistor and gate having a gate connected to the input terminal and a source connected to the high potential power supply line; a second CMOS inverter having a second N-channel transistor connected to the input terminal, a source connected to the low potential power supply line, and a drain connected to the drain of the second P-channel transistor. In, the first P
Let A be the ratio of the transistor width to the gate length of the channel transistor and the ratio of the transistor width to the gate length of the first N-channel transistor, and let A be the ratio of the transistor width to the gate length of the second P-channel transistor. If the ratio of the transistor width to the gate length of the second N-channel transistor is B, then the A is set to a value different from the B and the first CMOS inverter and the second CMOS
A semiconductor integrated circuit characterized in that an inverter has different threshold values.