JPS6315618U - - Google Patents
Info
- Publication number
- JPS6315618U JPS6315618U JP10857286U JP10857286U JPS6315618U JP S6315618 U JPS6315618 U JP S6315618U JP 10857286 U JP10857286 U JP 10857286U JP 10857286 U JP10857286 U JP 10857286U JP S6315618 U JPS6315618 U JP S6315618U
- Authority
- JP
- Japan
- Prior art keywords
- current mirror
- mirror circuit
- diode
- transistor
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
第１図と第２図は、本考案に係る電流ミラー型
増幅回路の実施例を示す図、第３図は、従来の電
流ミラー回路型の増幅回路である。
１：入力端子、２：出力端子、３乃至６：電流
ミラー回路、７：電流源、８：可変電流源。
1 and 2 are diagrams showing an embodiment of a current mirror type amplifier circuit according to the present invention, and FIG. 3 shows a conventional current mirror type amplifier circuit. 1: input terminal, 2: output terminal, 3 to 6: current mirror circuit, 7: current source, 8: variable current source.
Claims (1)
らなる第１の電流ミラー回路に、該第１の電流ミ
ラー回路の電流源用として第２と第３のトランジ
スタが接続され、該電流源用の第２と第３のトラ
ンジスタを電流ミラー回路の出力段とする第２の
電流ミラー回路を具え、該第１のダイオードと該
第２のトランジスタとの接続点を入力端子とし、
該第１のトランジスタと該第３のトランジスタと
の接続点を出力端子とし、該第１のダイオードの
カソード側に抵抗が接続され、その接続点に電流
源が接続されることによつて、所定の利得を得る
ことを特徴とする電流ミラー回路型の利得制御回
路。 (2) 前記第２の電流ミラー回路の出力段の該第
２と該第３のトランジスタの夫々が、電流ミラー
回路を形成し、該電流ミラー回路のバイアス側の
ダイオードが第３の電流ミラー回路の出力段の第
１と第２のトランジスタに接続され、該第２のト
ランジスタのエミツタが、該第１のダイオードの
カソードに接続された実用新案登録請求の範囲第
１項記載の電流ミラー回路型の利得制御回路。[Claims for Utility Model Registration] (1) A first current mirror circuit consisting of a first diode and a first transistor includes second and third transistors for current sources of the first current mirror circuit. a second current mirror circuit connected to each other, the second and third transistors for the current source serve as output stages of the current mirror circuit, and the connection point between the first diode and the second transistor is input. As a terminal,
A connection point between the first transistor and the third transistor is used as an output terminal, a resistor is connected to the cathode side of the first diode, and a current source is connected to the connection point, so that a predetermined voltage can be output. A current mirror circuit type gain control circuit characterized by obtaining a gain of . (2) Each of the second and third transistors in the output stage of the second current mirror circuit forms a current mirror circuit, and the diode on the bias side of the current mirror circuit forms a third current mirror circuit. The current mirror circuit type according to claim 1, wherein the current mirror circuit is connected to the first and second transistors of the output stage of the circuit, and the emitter of the second transistor is connected to the cathode of the first diode. gain control circuit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10857286U JPH0535613Y2 (en) | 1986-07-15 | 1986-07-15 | |
| US07/072,294 US4814724A (en) | 1986-07-15 | 1987-07-13 | Gain control circuit of current mirror circuit type |
| KR878711504U KR900010409Y1 (en) | 1986-07-15 | 1987-07-14 | Gain control circuit of current mirror type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10857286U JPH0535613Y2 (en) | 1986-07-15 | 1986-07-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6315618U true JPS6315618U (en) | 1988-02-02 |
| JPH0535613Y2 JPH0535613Y2 (en) | 1993-09-09 |
Family
ID=30985889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10857286U Expired - Lifetime JPH0535613Y2 (en) | 1986-07-15 | 1986-07-15 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0535613Y2 (en) |
| KR (1) | KR900010409Y1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013545363A (en) * | 2010-10-15 | 2013-12-19 | エス．シー． ジョンソン アンド サン、インコーポレイテッド | Application specific integrated circuit including motion detection system |
-
1986
- 1986-07-15 JP JP10857286U patent/JPH0535613Y2/ja not_active Expired - Lifetime
-
1987
- 1987-07-14 KR KR878711504U patent/KR900010409Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013545363A (en) * | 2010-10-15 | 2013-12-19 | エス．シー． ジョンソン アンド サン、インコーポレイテッド | Application specific integrated circuit including motion detection system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0535613Y2 (en) | 1993-09-09 |
| KR900010409Y1 (en) | 1990-11-15 |
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