JPS6421519U - - Google Patents
Info
- Publication number
- JPS6421519U JPS6421519U JP11472087U JP11472087U JPS6421519U JP S6421519 U JPS6421519 U JP S6421519U JP 11472087 U JP11472087 U JP 11472087U JP 11472087 U JP11472087 U JP 11472087U JP S6421519 U JPS6421519 U JP S6421519U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- limiter
- circuit
- collector
- npn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は、本考案に係るリミツタ回路の一実施
例を説明する為の回路図、第２図は、第１図の実
施例の出力波形を示す図、第３図は、本考案に係
るリミツタ回路の他の実施例、第４図は、従来の
リミツタ回路を示す回路図、第５図は、従来のリ
ミツタ回路の出力波形を示す図である。
３：出力端子、４：増幅回路、５：リミツタ回
路、７：電流源回路、Ｅ１，Ｅ２：バイアス電圧
源。
FIG. 1 is a circuit diagram for explaining an embodiment of the limiter circuit according to the present invention, FIG. 2 is a diagram showing the output waveform of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram for explaining an embodiment of the limiter circuit according to the present invention. Another embodiment of the limiter circuit, FIG. 4 is a circuit diagram showing a conventional limiter circuit, and FIG. 5 is a diagram showing an output waveform of the conventional limiter circuit. 3: output terminal, 4: amplifier circuit, 5: limiter circuit, 7: current source circuit, E 1 , E 2 : bias voltage source.
Claims (1)
して出力端子に接続されている第１のＮＰＮトラ
ンジスタと第１のＰＮＰトランジスタで形成され
、該出力段にリミツタ回路が設けられ、該リミツ
タ回路がエミツタを共通接続して該出力端子に接
続した第２のＮＰＮトランジスタと第２のＰＮＰ
トランジスタで形成され、且つ該第２のＮＰＮト
ランジスタと第２のＰＮＰトランジスタのベース
に夫々リミツタレベルを設定するバイアス電圧源
が接続されており、該増幅回路の出力のレベルが
所定のリミツタレベルに達すると、該増幅回路の
出力段のトランジスタに負帰還を掛けることによ
つて出力波形にリミツタを掛けることを特徴とす
るリミツタ回路。 (2) リミツタ回路が該第２のＮＰＮトランジス
タのコレクタに接続された第１のダイオードによ
つてバイアスされる第３のＰＮＰトランジスタを
具え、該第３のＰＮＰトランジスタのコレクタが
該第１のＰＮＰトランジスタのベースに接続され
、且つ該第２のＰＮＰトランジスタのコレクタに
接続された第２のダイオードによつてバイアスさ
れる第３のＮＰＮトランジスタを具え、該第３の
ＮＰＮトランジスタのコレクタが該第１のＮＰＮ
トランジスタのベースに接続されてなる実用新案
登録請求の範囲第１項記載のリミツタ回路。 (3) 前記増幅回路の出力段が、電流源回路とト
ランジスタで形成され、該増幅回路の出力段にリ
ミツタ回路が具えられ、該リミツタ回路が、エミ
ツタを共通接続して該出力端子に接続した第２の
ＮＰＮトランジスタと第２のＰＮＰトランジスタ
で形成され、且つ該第２のＮＰＮトランジスタと
第２のＰＮＰトランジスタのベースに夫々リミツ
タレベルを設定するバイアス電圧源が接続されて
おり、該第２のＮＰＮトランジスタのコレクタに
接続されたダイオードによつてバイアスされる第
４のＰＮＰトランジスタを具え、該第４のＰＮＰ
トランジスタのコレクタが、前記増幅回路の出力
段のトランジスタのバイアス回路に接続されて該
トランジスタに負帰還をかける実用新案登録請求
の範囲第１項記載のリミツタ回路。[Claims for Utility Model Registration] (1) The output stage of the amplifier circuit is formed of a first NPN transistor and a first PNP transistor whose emitters are connected in common and connected to the output terminal, A limiter circuit is provided, and the limiter circuit connects a second NPN transistor and a second PNP transistor whose emitters are commonly connected and connected to the output terminal.
A bias voltage source that sets a limiter level is connected to the bases of the second NPN transistor and the second PNP transistor, respectively, and when the level of the output of the amplifier circuit reaches a predetermined limiter level, A limiter circuit characterized in that a limiter is applied to an output waveform by applying negative feedback to a transistor in an output stage of the amplifier circuit. (2) the limiter circuit comprises a third PNP transistor biased by a first diode connected to the collector of the second NPN transistor, the collector of the third PNP transistor being biased by the first diode; a third NPN transistor connected to the base of the transistor and biased by a second diode connected to the collector of the second PNP transistor, the collector of the third NPN transistor being connected to the collector of the first PNP transistor; NPN of
The limiter circuit according to claim 1, which is connected to the base of a transistor. (3) The output stage of the amplifier circuit is formed of a current source circuit and a transistor, and the output stage of the amplifier circuit is provided with a limiter circuit, and the limiter circuit has emitters connected in common and connected to the output terminal. A bias voltage source is formed of a second NPN transistor and a second PNP transistor, and a bias voltage source for setting a limiter level is connected to the bases of the second NPN transistor and the second PNP transistor, respectively. a fourth PNP transistor biased by a diode connected to the collector of the transistor;
2. The limiter circuit according to claim 1, wherein the collector of the transistor is connected to a bias circuit of a transistor in the output stage of the amplifier circuit to apply negative feedback to the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114720U JPH0522978Y2 (en) | 1987-07-27 | 1987-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114720U JPH0522978Y2 (en) | 1987-07-27 | 1987-07-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6421519U true JPS6421519U (en) | 1989-02-02 |
| JPH0522978Y2 JPH0522978Y2 (en) | 1993-06-14 |
Family
ID=31355727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987114720U Expired - Lifetime JPH0522978Y2 (en) | 1987-07-27 | 1987-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0522978Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4717692B2 (en) * | 2006-04-14 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | Limiter circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63288506A (en) * | 1987-05-21 | 1988-11-25 | Toshiba Corp | Clipping circuit for multi-stage amplifier circuit |
-
1987
- 1987-07-27 JP JP1987114720U patent/JPH0522978Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63288506A (en) * | 1987-05-21 | 1988-11-25 | Toshiba Corp | Clipping circuit for multi-stage amplifier circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4717692B2 (en) * | 2006-04-14 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | Limiter circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0522978Y2 (en) | 1993-06-14 |
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