JPS6324799U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Figure 2 is a conventional sample and hold circuit diagram, Figure 3 is a clock waveform diagram for signal processing, Figure 4 a,
5b is an equivalent circuit diagram of FIG. 3, FIGS. 5a and 5b are equivalent circuit diagrams of FIG. 1, and FIG. 6 is a signal waveform diagram for explaining the operation. 14: Input terminal, 15: Output terminal, 18, 19
, 25: PNP transistor, 21, 22, 24
, 27: NPN transistor, 26: Hold capacitor.

Claims (1)

[Claims for Utility Model Registration] A first PNP transistor and a first NPN transistor each having an input signal applied to their bases, and connecting the emitters and collectors of the first PNP transistor and the first NPN transistor to each other, and connecting the bases with a sample period. A second PNP transistor to which a signal for setting the hold period is applied, a second NPN transistor, a third NPN transistor whose base is given the emitter potential of the pair of PNP transistors, and a third NPN transistor whose base is given the emitter potential of the pair of NPN transistors. 3PNP transistor, a capacitor having one electrode connected to the commonly connected emitters of the third NPN transistor and the third PNP transistor, and an output transistor having one electrode of the capacitor connected to the base and deriving an output signal. A sample hold circuit characterized by: