JPS6277914U - - Google Patents
Info
- Publication number
- JPS6277914U JPS6277914U JP17048285U JP17048285U JPS6277914U JP S6277914 U JPS6277914 U JP S6277914U JP 17048285 U JP17048285 U JP 17048285U JP 17048285 U JP17048285 U JP 17048285U JP S6277914 U JPS6277914 U JP S6277914U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- resistors
- base
- transistor
- bases
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の差動増幅回路の一実施例を示
す回路図、第２図は従来の差動増幅回路を示す回
路図である。
Ｑ１〜Ｑ６…トランジスタ、Ｒ１〜Ｒ４…抵抗
、１，２…入力端子、３…定電流源。
FIG. 1 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention, and FIG. 2 is a circuit diagram showing a conventional differential amplifier circuit. Q1 to Q6 ...transistor, R1 to R4 ...resistor, 1, 2...input terminal, 3...constant current source.
Claims (1)
、この両トランジスタのエミツタ共通接続点に接
続された定電流源と、前記第１、第２のトランジ
スタの各ベースと一対の入力端子との間にそれぞ
れ接続された抵抗Ｒ１，Ｒ２と、同じく前記第１
、第２のトランジスタの各ベースと電源との間に
それぞれ接続された抵抗Ｒ３，Ｒ４と、同じく前
記第１、第２のトランジスタの各ベースと所定電
位端との間にそれぞれコレクタ・エミツタ間が接
続された第３、第４のトランジスタと、前記第２
のトランジスタのベースの第４のトランジスタの
ベースとの間で互いに直列に接続された複数個の
ダイオードとからなることを特徴とする差動増幅
回路。 A first and second transistor forming a differential amplification pair, a constant current source connected to a common emitter connection point of both transistors, and a pair of input terminals connected to each base of the first and second transistors. Resistors R 1 and R 2 connected between the resistors R 1 and R 2 respectively, and the first
, resistors R 3 and R 4 respectively connected between the bases of the second transistors and the power supply, and collector-emitter resistors respectively connected between the bases of the first and second transistors and a predetermined potential terminal. third and fourth transistors connected between the transistors;
and a plurality of diodes connected in series between the base of the fourth transistor and the base of the fourth transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17048285U JPS6277914U (en) | 1985-11-06 | 1985-11-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17048285U JPS6277914U (en) | 1985-11-06 | 1985-11-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6277914U true JPS6277914U (en) | 1987-05-19 |
Family
ID=31105253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17048285U Pending JPS6277914U (en) | 1985-11-06 | 1985-11-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6277914U (en) |
-
1985
- 1985-11-06 JP JP17048285U patent/JPS6277914U/ja active Pending