JPH01159416U - - Google Patents
Info
- Publication number
- JPH01159416U JPH01159416U JP5423688U JP5423688U JPH01159416U JP H01159416 U JPH01159416 U JP H01159416U JP 5423688 U JP5423688 U JP 5423688U JP 5423688 U JP5423688 U JP 5423688U JP H01159416 U JPH01159416 U JP H01159416U
- Authority
- JP
- Japan
- Prior art keywords
- buffer circuit
- resistor
- buffer
- voltage
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案を実施したバツフア回路を示す
回路図である。第２図は従来例の回路図である。
３…第１バツフア回路、４…第２バツフア回路
、５…第３バツフア回路、１０…差動増幅回路、
Ｒ２…抵抗、Ｔｒ１Ａ，Ｔｒ２Ａ，Ｔｒ３Ａ…Ｎ
ＰＮトランジスタ、Ｔｒ１Ｂ，Ｔｒ２Ｂ，Ｔｒ３
Ｂ…ＰＮＰトランジスタ。
FIG. 1 is a circuit diagram showing a buffer circuit embodying the present invention. FIG. 2 is a circuit diagram of a conventional example. 3...First buffer circuit, 4...Second buffer circuit, 5...Third buffer circuit, 10...Differential amplifier circuit,
R2 ...Resistance, T r1 A, T r2 A, T r3 A...N
PN transistor, T r1 B, T r2 B, T r3
B...PNP transistor.
Claims (1)
持つコレクタ接地のＮＰＮトランジスタとＰＮＰ
トランジスタを前記ＮＰＮトランジスタのエミツ
タに前記ＰＮＰトランジスタのベースが接続され
るように組み合わせてなるバツフア回路を少くと
も２つ設け、その一方のバツフア回路の出力端を
抵抗を介して他方のバツフア回路の入力端に結合
し、且つ前記一方のバツフア回路の直流入力電圧
と他方のバツフア回路の直流出力電圧を等しくす
るための是正電圧を前記抵抗の両端に発生させる
手段を設けたことを特徴とするバツフア回路。 A common-collector NPN transistor and a PNP transistor each have a constant current source of the same capacity as an emitter load.
At least two buffer circuits are provided in which transistors are combined such that the base of the PNP transistor is connected to the emitter of the NPN transistor, and the output terminal of one buffer circuit is connected to the input terminal of the other buffer circuit through a resistor. A buffer circuit, characterized in that the buffer circuit is provided with means for generating a correction voltage across the resistor for equalizing the DC input voltage of the one buffer circuit and the DC output voltage of the other buffer circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5423688U JPH01159416U (en) | 1988-04-22 | 1988-04-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5423688U JPH01159416U (en) | 1988-04-22 | 1988-04-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01159416U true JPH01159416U (en) | 1989-11-06 |
Family
ID=31280171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5423688U Pending JPH01159416U (en) | 1988-04-22 | 1988-04-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01159416U (en) |
-
1988
- 1988-04-22 JP JP5423688U patent/JPH01159416U/ja active Pending
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