JPS62158933U - - Google Patents
Info
- Publication number
- JPS62158933U JPS62158933U JP4618286U JP4618286U JPS62158933U JP S62158933 U JPS62158933 U JP S62158933U JP 4618286 U JP4618286 U JP 4618286U JP 4618286 U JP4618286 U JP 4618286U JP S62158933 U JPS62158933 U JP S62158933U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- emitter
- transistors
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Amplifiers (AREA)
Description
第１図乃至第４図はそれぞれ本考案の異なる実
施例を示す回路図、第５図は従来例を示す回路図
である。
Ｑ１〜Ｑ７…トランジスタ、Ｒ１〜Ｒ３…抵抗
、ＶＢ…基準電圧、１０，１０′…定電流源。
1 to 4 are circuit diagrams showing different embodiments of the present invention, and FIG. 5 is a circuit diagram showing a conventional example. Q1-Q7...Transistor, R1-R3...Resistor, VB...Reference voltage, 10, 10'... Constant current source.
Claims (1)
ンジスタと、ベースに入力端子の形成された第２
のトランジスタとで差動対を構成し、前記第１お
よび第２のトランジスタの共通エミツタに第１の
電流供給手段が接続され、前記第１のトランジス
タのコレクタに負荷手段と第３のトランジスタに
よるエミツタホロワのベースが接続され、前記第
２のトランジスタのコレクタにダイオード接続さ
れた第４のトランジスタが順方向に接続され、前
記第４のトランジスタとカレントミラーを構成す
る第５のトランジスタのコレクタが前記第３のト
ランジスタのエミツタに接続され、前記第３のト
ランジスタのエミツタに出力端子の形成されてな
る２値信号出力回路において、前記第１および第
２のトランジスタと同一構造でありベースが前記
第１および第２のトランジスタの共通エミツタに
接続されかつコレクタが前記第２のトランジスタ
のコレクタに接続されてなる第６のトランジスタ
を具備し、前記第６のトランジスタのエミツタに
前記第１の電流供給手段と電流値が略々等しい第
２の電流供給手段を接続してなることを特徴とす
る２値信号出力回路。 (2) 第２のトランジスタのコレクタを接地し、
第６のトランジスタのコレクタ端に対し第４のト
ランジスタを順方向に直接接続してなることを特
徴とする実用新案登録請求の範囲第１項記載の２
値信号出力回路。[Claims for Utility Model Registration] (1) A first transistor whose base is connected to a reference power supply, and a second transistor whose base has an input terminal formed.
A first current supply means is connected to the common emitter of the first and second transistors, and a load means and an emitter follower formed of a third transistor are connected to the collector of the first transistor. A fourth transistor which is diode-connected to the collector of the second transistor is connected in the forward direction, and the collector of the fifth transistor forming a current mirror with the fourth transistor is connected to the collector of the third transistor. A binary signal output circuit is connected to an emitter of a transistor, and has an output terminal formed at an emitter of a third transistor, which has the same structure as the first and second transistors, and has a base connected to the first and second transistors. a sixth transistor connected to a common emitter of the second transistor and having a collector connected to the collector of the second transistor, the emitter of the sixth transistor being connected to the first current supply means and a current value; A binary signal output circuit characterized in that the circuit is connected to a second current supply means having substantially equal currents. (2) Ground the collector of the second transistor,
Claim 2 of Claim 1, characterized in that the fourth transistor is directly connected in the forward direction to the collector end of the sixth transistor.
Value signal output circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4618286U JPS62158933U (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4618286U JPS62158933U (en) | 1986-03-31 | 1986-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62158933U true JPS62158933U (en) | 1987-10-08 |
Family
ID=30865607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4618286U Pending JPS62158933U (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62158933U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01183212A (en) * | 1988-01-18 | 1989-07-21 | Sony Corp | Level conversion circuit |
| WO2018012083A1 (en) * | 2016-07-11 | 2018-01-18 | ソニー株式会社 | Switching circuit, automatic gain control circuit and phase synchronization circuit |
-
1986
- 1986-03-31 JP JP4618286U patent/JPS62158933U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01183212A (en) * | 1988-01-18 | 1989-07-21 | Sony Corp | Level conversion circuit |
| WO2018012083A1 (en) * | 2016-07-11 | 2018-01-18 | ソニー株式会社 | Switching circuit, automatic gain control circuit and phase synchronization circuit |
| JPWO2018012083A1 (en) * | 2016-07-11 | 2019-04-25 | ソニー株式会社 | Switching circuit, automatic gain control circuit and phase synchronization circuit |
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