WO2018012083A1 - Switching circuit, automatic gain control circuit and phase synchronization circuit - Google Patents

Switching circuit, automatic gain control circuit and phase synchronization circuit Download PDF

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Publication number
WO2018012083A1
WO2018012083A1 PCT/JP2017/016371 JP2017016371W WO2018012083A1 WO 2018012083 A1 WO2018012083 A1 WO 2018012083A1 JP 2017016371 W JP2017016371 W JP 2017016371W WO 2018012083 A1 WO2018012083 A1 WO 2018012083A1
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WIPO (PCT)
Prior art keywords
bipolar transistor
signal
base
voltage
connection point
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Application number
PCT/JP2017/016371
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French (fr)
Japanese (ja)
Inventor
隼 永田
暁 新家
法男 小路
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ソニー株式会社
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Priority to JP2018527404A priority Critical patent/JP6891888B2/en
Publication of WO2018012083A1 publication Critical patent/WO2018012083A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • This technology relates to a switching circuit, an automatic gain control circuit, and a phase synchronization circuit.
  • the present invention relates to a switching circuit, an automatic gain control circuit, and a phase synchronization circuit including a transistor that shifts to an on state or an off state depending on a signal level.
  • an AGC Automatic Gain Control circuit that dynamically controls a gain for a signal is used in an acoustic device or a communication device in order to keep the amplitude of the signal constant.
  • the AGC circuit generally includes a detection circuit that outputs a control voltage corresponding to the amplitude of the signal, and a variable gain amplifier that amplifies the signal with a gain corresponding to the control voltage.
  • the detection circuit includes, for example, a comparator that compares an input signal with a reference signal, a transistor that is turned on / off according to the comparison result, a recover current source, and an attack current source.
  • the recovery current source and a capacitor that generates a control voltage by charging and discharging a control current from the attack current source controlled based on the comparison result are provided (for example, see Patent Document 1).
  • One end of this capacitor is connected to the recovery current source and the connection point of the transistor and the variable gain amplifier.
  • the time constant Tc of the AGC circuit described above is proportional to the capacitance C of the capacitor and inversely proportional to the control current Icon from the transistor. If this time constant Tc is increased, the high-frequency cutoff frequency can be reduced to reduce the AC component in the signal and to improve the signal quality. In order to increase the time constant Tc while the capacitance C is constant, the control current Icon may be decreased. However, when the control current Icon is reduced, the leakage current that flows when the transistor is off is relatively increased. Due to the increase in the leakage current, there is a problem that the control voltage for controlling the gain becomes a value different from the design value, and the gain deviates from the assumed value.
  • MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
  • the influence of the leakage current can be reduced.
  • the low frequency noise (1 / f noise) is larger than that of the bipolar transistor.
  • This technology was created in view of such a situation, and in an AGC circuit including a transistor that shifts to an on state or an off state depending on a signal level, low-frequency noise is reduced while reducing leakage current.
  • the purpose is to do.
  • the present technology has been made to solve the above-described problems.
  • the first aspect of the present technology is a cascode connection between the first bipolar transistor and the first bipolar transistor at a connection point, and a threshold voltage is set.
  • the second bipolar transistor to which a constant bias voltage not lower than the base is applied is compared with the input signal and a predetermined reference signal, and a pair of differential output signals indicating the comparison result are obtained from the first bipolar transistor.
  • the switching circuit includes a base and a comparison unit that outputs to the connection point. As a result, the cascode-connected first and second bipolar transistors are controlled by a pair of differential output signals.
  • the input stage of the comparison unit may include a pair of differential transistors.
  • a pair of differential output signals are output by the pair of differential transistors.
  • the pair of differential transistors may be bipolar transistors.
  • a pair of differential output signals are output by the pair of bipolar transistors.
  • the pair of differential transistors may be MOS (Metal Oxide Semiconductor) transistors.
  • MOS Metal Oxide Semiconductor
  • a first bipolar transistor and a second bias voltage that is cascode-connected to the first bipolar transistor at a connection point and a constant bias voltage not lower than a threshold voltage is applied to a base.
  • a comparator that compares the bipolar transistor with an input signal and a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point;
  • An automatic gain comprising: a recover current source for supplying a current; a capacitor connected to the recover current source and the second bipolar transistor; and a variable gain amplifier that changes a gain according to a charge / discharge voltage of the capacitor. It is a control circuit. As a result, the gain is changed according to the charge / discharge voltage of the capacitor connected to the cascode-connected bipolar transistor and the recovery current source.
  • the input of the comparison unit may be the input of the variable gain amplifier.
  • the input of the comparison unit may be the output of the variable gain amplifier.
  • a third aspect of the present technology includes a detector that detects a phase difference and a frequency difference between an input signal and a feedback signal and outputs first and second output signals indicating the detection result;
  • a first comparison for comparing a signal obtained by inverting the first output signal and outputting a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the first connection point A third bipolar transistor, and a cascode connection to the third bipolar transistor at the second connection point, and a constant bias voltage not lower than the threshold voltage is applied to the base voltage.
  • a second comparator for outputting to the base of the transistor and the second connection point; a capacitor connected to the connection point of the second and fourth bipolar transistors; and a frequency corresponding to the charge / discharge voltage of the capacitor
  • a phase controlled circuit comprising: a voltage-controlled oscillator that outputs a periodic signal; and a frequency divider that divides the periodic signal and feeds it back to the detector as the feedback signal.
  • an AGC circuit including a transistor can have an excellent effect of reducing a leakage current while reducing low-frequency noise. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
  • 12 is a timing chart illustrating an example of fluctuations in input voltage and output voltage in the second embodiment of the present technology.
  • 12 is a timing chart illustrating an example of the operation of the AGC circuit according to the second embodiment of the present technology.
  • 12 is a flowchart illustrating an example of an operation of the AGC circuit according to the second embodiment of the present technology.
  • It is a block diagram showing an example of 1 composition of an electronic device in a 3rd embodiment of this art.
  • It is a circuit diagram showing an example of 1 composition of a charge pump in a 3rd embodiment of this art.
  • 12 is a timing chart illustrating an example of an operation of the charge pump according to the third embodiment of the present technology.
  • FIG. 1 is a circuit diagram showing a configuration example of the current switching circuit 240 according to the first embodiment.
  • the current switching circuit 240 includes a comparison unit 250 and bipolar transistors 241 and 242. These bipolar transistors 241 and 242 are, for example, npn type.
  • a constant bias voltage Vb is applied to the base of the bipolar transistor 241.
  • the bias voltage Vb is set to a value that does not fall below the threshold voltage of the bipolar transistor 241.
  • the collector of the bipolar transistor 241 is connected to the output terminal of the current switching circuit 240.
  • the bipolar transistor 241 is cascode-connected to the bipolar transistor 242.
  • the bipolar transistor 242 is an example of a first transistor described in the claims.
  • the bipolar transistor 241 is an example of a second transistor described in the claims.
  • the comparison unit 250 compares the input voltage Vin and the reference voltage Vref.
  • the comparison unit outputs a differential output signal indicating the comparison result to the base of the bipolar transistor 242 and the connection point of the bipolar transistors 241 and 242.
  • the output voltage Vop of the positive differential output signal is output to the base of the bipolar transistor 242.
  • the output voltage Von of the negative differential output signal is output to the connection point of the bipolar transistors 241 and 242.
  • the comparison unit 250 includes a constant current source 260, switches 270 and 280, and bipolar transistors 251 and 252. These bipolar transistors 251 and 252 are, for example, npn type.
  • the constant current source 260 supplies a constant current.
  • the switch 270 shifts to either a conduction state (ie, an on state) or a non-conduction state (ie, an off state) according to the value of the input voltage Vin with respect to the reference voltage Vref. For example, when the input voltage Vin is higher than the reference voltage Vref, the switch 270 shifts to an off state.
  • the switch 280 operates exclusively with the switch 270.
  • the switches 270 and 280 are an example of a pair of differential transistors described in the claims.
  • the emitter of the bipolar transistor 251 is grounded, and the collector is connected to the switch 270.
  • the collector and base of the bipolar transistor 251 are short-circuited (so-called diode connection).
  • the base of the bipolar transistor 251 is also connected to the base of the bipolar transistor 242.
  • Bipolar transistor 252 The emitter of the bipolar transistor 252 is grounded, and the collector is connected to the switch 280.
  • Bipolar transistor 252 is diode-connected, and its base is also connected to the connection point of bipolar transistors 241 and 242.
  • the bipolar transistors 241 and 242 are turned off.
  • the bipolar transistors 241 and 242 are turned on. Since the bipolar transistors 241 and 242 are cascode-connected, the output resistance viewed from the output terminal of the current switching circuit 240 is higher than that in the comparative example when switching is performed with only one bipolar transistor. Thereby, the leakage current can be reduced. Further, since switching is performed by the bipolar transistors 241 and 242, the 1 / f noise can be reduced as compared with the case where the MOS transistor is used.
  • the output resistance is higher than when only one transistor is used. . Thereby, the leakage current of those transistors can be reduced.
  • FIG. 2 is a block diagram illustrating a configuration example of the electronic device 100 according to the second embodiment.
  • the electronic device 100 is a device that processes an analog signal, and includes an analog signal output unit 110, an AGC circuit 200, and a signal processing unit 120.
  • As the electronic device 100 for example, a wireless communication device, an audio device, a video reproduction device, or the like is assumed.
  • the analog signal output unit 110 outputs an analog signal of the input voltage Vin to the AGC circuit 200 via the signal line 119.
  • the analog signal output unit 110 for example, an antenna or a sensor (such as an image sensor or a microphone) in a wireless communication device is assumed.
  • the AGC circuit 200 increases or decreases the input voltage Vin of the signal by a gain corresponding to the amplitude of the analog signal.
  • the AGC circuit 200 supplies the voltage whose amplitude has been adjusted to the signal processing unit 120 via the signal line 209 as the output voltage Vout.
  • the AGC circuit 200 is an example of an automatic gain control circuit described in the claims.
  • the signal processing unit 120 performs predetermined processing on the analog signal of the output voltage Vout.
  • the signal processing unit 120 executes, for example, AD conversion processing, decoding processing for decoding a radio signal, and the like.
  • FIG. 3 is a circuit diagram showing a configuration example of the AGC circuit 200 according to the second embodiment.
  • the AGC circuit 200 includes a variable gain amplifier 210 and a peak detection circuit 220.
  • the peak detection circuit 220 includes a reference voltage supply unit 221, a capacitor 222, a bias voltage supply unit 230, and a current switching circuit 240.
  • the configuration of the current switching circuit 240 is the same as that of the first embodiment except that a recover current source 290 that supplies a constant current is added. This recovering current source 290 is connected to the bipolar transistor 241 and the output terminal.
  • the reference voltage supply source 221 supplies a lower limit threshold level of the input voltage signal Vin to the comparison unit 250 in order to obtain a desired amplitude of the output signal Vout.
  • the bias voltage supply unit 230 supplies a constant bias voltage Vb to the current switching circuit 240.
  • One end of the capacitor 222 is connected to the output terminal of the current switching circuit 240 and the variable gain amplifier 210.
  • the capacitor 222 charges and discharges the control current Icon from the output terminal of the current switching circuit 240 to generate the control voltage Vc.
  • the variable gain amplifier 210 changes the gain according to the control voltage Vc. For example, the higher the control voltage Vc, the larger the gain.
  • the variable gain amplifier 210 increases or decreases the input voltage Vin with a gain corresponding to the control voltage Vc, and outputs the increased or decreased voltage to the signal processing unit 120 as the output voltage Vout.
  • FIG. 4 is a circuit diagram showing a configuration example of the peak detection circuit 220 according to the second embodiment.
  • the constant current source 260 includes, for example, bipolar transistors 261 and 262. Further, a bipolar transistor 271 is used as the switch 270, and a bipolar transistor 281 is used as the switch 280.
  • the bias voltage supply unit 230 includes bipolar transistors 231 and 233 and a resistor 232.
  • the recovering current source 290 includes a MOS (Metal Oxide Semiconductor) transistor 291.
  • MOS Metal Oxide Semiconductor
  • the bipolar transistors 231, 261, 262, 271 and 281 are, for example, pnp type, and the bipolar transistor 233 is, for example, npn type.
  • the MOS transistor 291 is, for example, P type.
  • the emitter of the bipolar transistor 261 is connected to the power supply, and the base is connected to the bases of the bipolar transistors 262 and 231.
  • the bipolar transistor 261 is diode-connected, and its collector is connected to a constant current source (not shown) that supplies a reference current Iref.
  • the emitter of the bipolar transistor 262 is connected to the power supply, and the collector is connected to the emitters of the bipolar transistors 271 and 281.
  • the reference current Iref is duplicated by such a current mirror circuit.
  • the input voltage Vin is input to the base of the bipolar transistor 271, and the collector is connected to the bipolar transistor 251.
  • the reference voltage Vref is input to the base of the bipolar transistor 281, and the collector is connected to the bipolar transistor 252.
  • the emitter of the bipolar transistor 231 is connected to the power supply, and the collector is connected to the resistor 232 and the base of the bipolar transistor 241.
  • the bipolar transistor 233 is diode-connected and is inserted between the resistor 232 and the ground terminal.
  • the bipolar transistor 231 generates a current that duplicates the reference current Iref, and the current, the resistor 232, and the bipolar transistor 233 generate a bias voltage Vb.
  • the MOS transistor 291 is diode-connected, and its drain is connected to the bipolar transistor 241 and the capacitor 222.
  • the comparison unit 250 generates the output voltages Vop and Von using a current that is a copy of the reference current Iref.
  • the bias voltage supply unit 230 generates the bias voltage Vb using a current that is a copy of the reference current Iref. For this reason, even if the reference current Iref varies depending on conditions such as process, voltage, and temperature (PVT conditions), the bias voltage Vb, the output voltages Vop, and Von increase or decrease to the same extent according to the current.
  • FIG. 5 is a diagram illustrating an example of the state of the current switching circuit 240 when the input voltage Vin is higher than the reference voltage Vref in the second embodiment.
  • the current flowing through switch 270 and bipolar transistor 251 decreases, and the current flowing through switch 280 and bipolar transistor 252 increases.
  • the base potential (Vop) of the bipolar transistor 242 decreases, and the emitter potential (Von) of the bipolar transistor 241 increases.
  • the bipolar transistor 242 shifts to an off state due to a decrease in base potential. Further, since the bias voltage Vb is applied to the base of the bipolar transistor 241, the base-emitter voltage of the bipolar transistor 241 becomes less than the threshold voltage. For this reason, the bipolar transistor 241 is also turned off.
  • the current Ir of the recover current source 290 is almost output as the control current Icon, and the capacitor 222 is charged / discharged by the current. As a result, the control voltage Vc increases with time.
  • FIG. 6 is a diagram illustrating an example of the state of the current switching circuit 240 when the input voltage Vin is equal to or lower than the reference voltage Vref in the second embodiment.
  • the current flowing through switch 270 and bipolar transistor 251 increases, and the current flowing through switch 280 and bipolar transistor 252 decreases.
  • the base potential (Vop) of the bipolar transistor 242 increases, and the emitter potential (Von) of the bipolar transistor 241 decreases.
  • the bipolar transistor 242 shifts to the on state due to the rise of the base potential. Further, since the bias voltage Vb is applied to the base of the bipolar transistor 241, the base-emitter voltage of the bipolar transistor 241 becomes equal to or higher than the threshold voltage. For this reason, the bipolar transistor 241 is also turned on.
  • the accumulated charge of the capacitor 222 is extracted by the attack current Ia flowing through the bipolar transistors 241 and 242 in the on state, and the control voltage Vc decreases with time.
  • FIG. 7 is a circuit diagram showing a configuration example of the AGC circuit in the comparative example.
  • the control current Icon in order to increase the time constant Tc, the control current Icon may be reduced or the capacitance C may be increased from the above equation. Increasing the capacitance C increases the size of the capacitor and increases the circuit layout area. In order to increase the time constant Tc without increasing the capacitance C, the control current Icon may be decreased. However, when the control current Icon is reduced, the leakage current that flows when the transistor is off may be relatively increased. As the leakage current increases, the attack current Ia for extracting the current from the capacitor becomes smaller than a desired value, and the operating point of the AGC circuit becomes a value different from the design value.
  • the current switching circuit 240 bipolar transistors 241 and 242 connected in cascode are provided at the output stage of the comparison unit 250.
  • the output resistance viewed from the output terminal of the current switching circuit 240 is higher than that in the comparative example when switching is performed with only one bipolar transistor. Thereby, the leakage current can be made smaller than that of the comparative example. Further, since switching is performed by the bipolar transistors 241 and 242, the 1 / f noise can be reduced as compared with the case where the MOS transistor is used.
  • the transistors in the AGC circuit 200 are preferably bipolar transistors from the viewpoint of reducing 1 / f noise, but some of them may be MOS transistors.
  • FIG. 8 is a timing chart showing an example of fluctuations in the input voltage Vin and the output voltage Vout in the second embodiment.
  • the AGC circuit 200 increases / decreases the input voltage Vin with a relatively large gain and outputs it as the output voltage Vout.
  • the amplitude of the input voltage Vin has increased after time T2.
  • the AGC circuit 200 increases / decreases the input voltage Vin with a relatively small gain and outputs it as the output voltage Vout.
  • FIG. 9 is a timing chart showing an example of the operation of the AGC circuit 200 according to the second embodiment.
  • the input voltage Vin is higher than the reference voltage Vref.
  • the AGC circuit 200 charges and discharges the capacitor 222 with the current Ir from the recovering current source, and the control voltage Vc increases with time.
  • the input voltage Vin is equal to or lower than the reference voltage Vref.
  • the AGC circuit 200 discharges the capacitor 222 with the attack current Ia, and the control voltage Vc decreases with time.
  • the control voltage Vc corresponding to the integrated value of the current represented by the right side or the left side of the above equation is generated by the capacitor 222. If the leakage current can be reduced, the control current Icon can be reduced, and a large time constant Tc can be realized with a small capacitance C.
  • FIG. 10 is a flowchart showing an example of the operation of the AGC circuit 200 according to the second embodiment. This operation starts, for example, when an analog signal is input to the AGC circuit 200.
  • the AGC circuit 200 determines whether or not the input voltage Vin is higher than the reference voltage Vref (step S901). When the input voltage Vin is equal to or lower than the reference voltage Vref (step S901: No), the AGC circuit 200 gradually decreases the control voltage Vc (step S902). The gain decreases as the control voltage Vc decreases.
  • step S901 when the input voltage Vin is higher than the reference voltage Vref (step S901: Yes), the AGC circuit 200 gradually increases the control voltage Vc (step S903).
  • the gain increases as the control voltage Vc increases.
  • step S902 or S903 the AGC circuit 200 increases or decreases the input voltage Vin according to the gain (step S904).
  • the two bipolar transistors that are turned on / off by the comparison unit 250 are cascode-connected, so that the output resistance is higher than when only one transistor is used. . Thereby, the leakage current of those transistors can be reduced.
  • the peak detection circuit 220 performs the feedforward control for generating the control voltage Vc from the input voltage Vin before increase / decrease, but can also be realized by feedback control.
  • FIG. 11 is a block diagram illustrating a configuration example of the AGC circuit 200 according to a modification of the second embodiment.
  • the variable gain amplifier 210 inputs (in other words, feeds back) the output voltage Vout to the peak detection circuit 220. Then, the peak detection circuit 220 compares the output voltage Vout with the reference voltage Vref and generates a control voltage Vc.
  • variable gain amplifier 210 feeds back the output voltage Vout to the peak detection circuit 220, so that feedback control can be performed.
  • the cascode-connected transistor is provided in the AGC circuit 200. However, if the circuit performs a switching operation, a cascode-connected transistor is provided in a circuit other than the AGC circuit 200 such as a charge pump. You can also.
  • the electronic device according to the second embodiment is different from the first embodiment in that a cascode-connected transistor is provided in the charge pump.
  • FIG. 12 is a block diagram illustrating a configuration example of the electronic device 101 according to the third embodiment.
  • the electronic device 101 includes a phase synchronization circuit 130 and a signal processing unit 140.
  • the phase synchronization circuit 130 is used for the purpose of stabilizing the oscillation frequency of the voltage controlled oscillator using the external clock CLKin having a low phase noise as a reference signal.
  • the clock signal CLKin is generated by a crystal oscillator or the like.
  • the phase synchronization circuit 130 includes a phase / frequency detector 131, a charge pump 300, a voltage controlled oscillator 132, and a frequency divider 133.
  • the phase / frequency detector 131 detects a phase difference and a frequency difference between the clock signal CLKin and the clock signal CLKfb fed back from the frequency divider 133.
  • the phase / frequency detector 131 supplies output signals Voa and Vob indicating the detection result to the charge pump 300.
  • the phase / frequency detector 131 is an example of the detector described in the claims.
  • the charge pump 300 generates the control voltage Vc according to the phase difference and the frequency difference.
  • the charge pump 300 supplies the control voltage Vc to the voltage controlled oscillator 132.
  • the voltage controlled oscillator 132 generates a signal having a frequency corresponding to the control voltage Vc as the periodic signal VCOout.
  • the voltage controlled oscillator 132 supplies the periodic signal VCOout to the signal processing unit 140 and the frequency divider 133.
  • the frequency divider 133 divides the periodic signal VCOout by a predetermined frequency division ratio.
  • the frequency divider 133 feeds back the frequency-divided signal to the phase / frequency detector 131 as the clock signal CLKfb.
  • the signal processing unit 140 performs predetermined signal processing in synchronization with the periodic signal VCOout.
  • FIG. 13 is a circuit diagram showing a configuration example of the charge pump 300 according to the third embodiment.
  • the charge pump 300 includes inverters 310 and 311, constant current sources 321 and 335, bipolar transistors 322 to 325, and bipolar transistors 331 to 334.
  • the charge pump 300 includes bipolar transistors 341 to 344 and a capacitor 350.
  • the bipolar transistors 322, 324, 331, 333, 341, and 342 are, for example, pnp type, and the bipolar transistors 323, 325, 332, 334, 343, and 344 are, for example, npn type.
  • the emitters of the bipolar transistors 322 and 324 are connected to the constant current source 321.
  • the base of the bipolar transistor 322 is connected to the output terminal of the inverter 310, and the output signal Vob is input to the base of the bipolar transistor 324.
  • the collector of bipolar transistor 322 is connected to the collector of bipolar transistor 323, and the collector of bipolar transistor 324 is connected to the collector of bipolar transistor 325.
  • Inverter 310 inverts output signal Vob.
  • the collector of the bipolar transistor 323 is connected to the base of the bipolar transistor 323 itself and the base of the bipolar transistor 344.
  • the collector of the bipolar transistor 325 is connected to the base of the bipolar transistor 325 itself and the connection point of the bipolar transistors 343 and 344.
  • the emitters of bipolar transistors 323 and 325 are grounded.
  • the emitters of the bipolar transistors 332 and 334 are connected to a constant current source 335.
  • the base of the bipolar transistor 332 is connected to the output terminal of the inverter 311, and the output signal Voa is input to the base of the bipolar transistor 334.
  • the collector of bipolar transistor 332 is connected to the collector of bipolar transistor 331, and the collector of bipolar transistor 334 is connected to the collector of bipolar transistor 333.
  • the inverter 311 inverts the output signal Voa.
  • the collector of the bipolar transistor 333 is connected to the base of the bipolar transistor 333 itself and the base of the bipolar transistor 341.
  • the collector of the bipolar transistor 331 is connected to the base of the bipolar transistor 331 itself and the connection point of the bipolar transistors 341 and 342.
  • the emitters of bipolar transistors 331 and 333 are connected to a power source.
  • the bipolar transistors 341 and 342 are cascode-connected, and the bipolar transistors 343 and 344 are also cascode-connected.
  • the emitter of the bipolar transistor 341 is connected to the power supply, and the emitter of the bipolar transistor 344 is grounded.
  • the collector of bipolar transistor 342 is connected to the collector of bipolar transistor 343.
  • a bias voltage Vb1 is applied to the base of the bipolar transistor 342, and a bias voltage Vb2 is applied to the base of the bipolar transistor 343.
  • a circuit (not shown) for supplying these bias voltages is arranged in the charge pump 300.
  • One end of the capacitor 350 is connected to the connection point of the bipolar transistors 342 and 343 and the output terminal of the charge pump 300, and the other end is grounded.
  • a circuit including the constant current source 321, the bipolar transistors 322 to 325, and the bipolar transistors 343 and 344 has the same function as the current switching circuit 240 of FIG.
  • the circuit composed of the constant current source 335, the bipolar transistors 331 to 334, and the bipolar transistors 341 and 342 has the same function as the current switching circuit 240 of FIG.
  • Each of these current switching circuits is turned on and off according to the values of the output signals Voa and Vob.
  • the bipolar transistors 341 to 344 are examples of first to fourth transistors recited in the claims.
  • the capacitor 222 is charged / discharged by the control current Icon, and the charge / discharge voltage is output as the control voltage Vc.
  • FIG. 14 is a timing chart showing an example of the operation of the charge pump 300 according to the third embodiment. Assume that the output signal Voa shifts from the low level to the high level at the timing T10, and the output signal Vob shifts from the low level to the high level at the subsequent timing T11. Further, it is assumed that the output signals Voa and Vob are shifted to the low level at the subsequent timing T12.
  • the bipolar switches 341 and 342 are turned on between the timing T10 and the timing T12, and the current Id1 increases.
  • the bipolar switches 343 and 344 are turned on between the timing T11 and the timing T12, and the current Id2 increases.
  • the leakage current is reduced during the off-state period, and the current Id1 becomes almost zero.
  • the bipolar transistors 343 and 344 are also cascode-connected, the leakage current is reduced during the off-state period, and the current Id2 becomes almost zero.
  • a leakage current occurs in the comparative example in which the cascode connection is not performed.
  • the dotted lines in FIG. 14 are the current and voltage of the comparative example.
  • control current Icon which is the difference between the currents Id1 and Id2 increases from the timing T10 to the timing T11.
  • the increase amount of the control current Icon is reduced due to the generation of the leakage current.
  • the capacitor 350 is charged by the control current Icon that flows between the timing T10 and the timing T11, and the control voltage Vc increases.
  • the amount of increase in the control voltage Vc is reduced due to the occurrence of leakage current.
  • the cascode-connected transistor is provided in the charge pump 300, the leakage current of the charge pump 300 can be reduced.
  • this technique can also take the following structures.
  • a first bipolar transistor A second bipolar transistor that is cascode-connected to the first bipolar transistor at a connection point and that has a constant bias voltage not applied below a threshold voltage applied to a base;
  • a comparison unit that compares the input signal with a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point;
  • a recover current source for supplying a constant current;
  • a capacitor connected to the recovering current source and the second bipolar transistor;
  • An automatic gain control circuit comprising: a variable gain amplifier that changes a gain according to a charge / discharge voltage of the capacitor.
  • a detector that detects a phase difference and a frequency difference between the input signal and the feedback signal and outputs first and second output signals indicating the detection result;
  • a second bipolar transistor that is cascode-connected to the first bipolar transistor at a first connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
  • a pair of differential output signals indicating the comparison result by comparing the first output signal and a signal obtained by inverting the first output signal are obtained from the base of the first bipolar transistor and the first connection point.
  • a first comparison unit that outputs to A third bipolar transistor;
  • a fourth bipolar transistor that is cascode-connected to the third bipolar transistor at a second connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
  • a pair of differential output signals indicating the comparison result by comparing the second output signal with a signal obtained by inverting the second output signal and the base of the third bipolar transistor and the second connection point
  • a second comparison unit for outputting to A capacitor connected to a connection point of the second and fourth bipolar transistors;
  • a voltage-controlled oscillator that outputs a periodic signal having a frequency corresponding to the charge / discharge voltage of the capacitor;
  • a phase synchronization circuit comprising: a frequency divider that divides the periodic signal and feeds it back to the detector as the feedback signal.

Abstract

The present invention reduces a leak current while reducing low-frequency noise in an AGC circuit provided with a transistor that shifts to an on state or an off state according to the level of a signal. A switching circuit is provided with a first bipolar transistor, a second bipolar transistor and a comparison unit. The second bipolar transistor is cascode-connected to the first bipolar transistor at a connection point, and a fixed bypass voltage that is not less than a threshold voltage is applied to a base thereof. The comparison unit compares an input signal and a predetermined reference signal, and outputs a pair of differential output signals indicating the result of the comparison to a base of the first bipolar transistor and the connection point.

Description

スイッチング回路、自動利得制御回路および位相同期回路Switching circuit, automatic gain control circuit, and phase synchronization circuit
　本技術は、スイッチング回路、自動利得制御回路および位相同期回路に関する。詳しくは、信号のレベルに応じてオン状態またはオフ状態に移行するトランジスタを備えるスイッチング回路、自動利得制御回路および位相同期回路に関する。 This technology relates to a switching circuit, an automatic gain control circuit, and a phase synchronization circuit. Specifically, the present invention relates to a switching circuit, an automatic gain control circuit, and a phase synchronization circuit including a transistor that shifts to an on state or an off state depending on a signal level.
　従来より、音響機器や通信機器などにおいて、信号の振幅を一定に維持するために、その信号に対するゲインを動的に制御するＡＧＣ（Automatic Gain Control）回路が用いられている。このＡＧＣ回路は、一般に、信号の振幅に応じた制御電圧を出力する検波回路と、その制御電圧に応じたゲインで信号を増幅する可変ゲインアンプとを備える。この検波回路には、例えば、入力信号と参照信号とを比較する比較器と、その比較結果に応じてオンオフするトランジスタと、リカバー電流源とアタック電流源とが設けられる。そのリカバー電流源と、比較結果により制御されたアタック電流源による制御電流を充放電して制御電圧を生成するコンデンサとが設けられる（例えば、特許文献１参照。）。このコンデンサの一端は、リカバー電流源およびトランジスタの接続点と可変ゲインアンプとに接続される。 Conventionally, an AGC (Automatic Gain Control) circuit that dynamically controls a gain for a signal is used in an acoustic device or a communication device in order to keep the amplitude of the signal constant. The AGC circuit generally includes a detection circuit that outputs a control voltage corresponding to the amplitude of the signal, and a variable gain amplifier that amplifies the signal with a gain corresponding to the control voltage. The detection circuit includes, for example, a comparator that compares an input signal with a reference signal, a transistor that is turned on / off according to the comparison result, a recover current source, and an attack current source. The recovery current source and a capacitor that generates a control voltage by charging and discharging a control current from the attack current source controlled based on the comparison result are provided (for example, see Patent Document 1). One end of this capacitor is connected to the recovery current source and the connection point of the transistor and the variable gain amplifier.
特開２００７－２５５９０９号公報JP 2007-255909 A
　上述のＡＧＣ回路の時定数Ｔｃは、コンデンサの容量Ｃに比例し、トランジスタからの制御電流Ｉｃｏｎに反比例する。この時定数Ｔｃを大きくすれば、高周波遮断周波数を小さくして信号における交流成分を低減し、信号品質を高くすることができる。容量Ｃが一定の下で時定数Ｔｃを大きくするには、制御電流Ｉｃｏｎを小さくすればよい。しかしながら、制御電流Ｉｃｏｎを小さくすると、トランジスタがオフ状態の際に流れるリーク電流が相対的に大きくなる。そして、そのリーク電流の増大により、ゲインを制御する制御電圧が設計値と異なる値になり、ゲインが想定値から外れてしまうという問題がある。 The time constant Tc of the AGC circuit described above is proportional to the capacitance C of the capacitor and inversely proportional to the control current Icon from the transistor. If this time constant Tc is increased, the high-frequency cutoff frequency can be reduced to reduce the AC component in the signal and to improve the signal quality. In order to increase the time constant Tc while the capacitance C is constant, the control current Icon may be decreased. However, when the control current Icon is reduced, the leakage current that flows when the transistor is off is relatively increased. Due to the increase in the leakage current, there is a problem that the control voltage for controlling the gain becomes a value different from the design value, and the gain deviates from the assumed value.
　ここで、バイポーラトランジスタよりもリーク電流が低いＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）をトランジスタとして用いれば、リーク電流の影響を緩和することができる。ただし、ＭＯＳＦＥＴでは、低域ノイズ（１／ｆノイズ）がバイポーラトランジスタよりも大きくなってしまう。このように、上述の従来技術では、低域ノイズを低減しつつ、リーク電流を抑制することが困難である。 Here, if a MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor) having a leakage current lower than that of the bipolar transistor is used as the transistor, the influence of the leakage current can be reduced. However, in the MOSFET, the low frequency noise (1 / f noise) is larger than that of the bipolar transistor. Thus, with the above-described conventional technology, it is difficult to suppress the leakage current while reducing the low-frequency noise.
　本技術はこのような状況に鑑みて生み出されたものであり、信号のレベルに応じてオン状態またはオフ状態に移行するトランジスタを備えるＡＧＣ回路において、低域ノイズを低減しつつ、リーク電流を低減することを目的とする。 This technology was created in view of such a situation, and in an AGC circuit including a transistor that shifts to an on state or an off state depending on a signal level, low-frequency noise is reduced while reducing leakage current. The purpose is to do.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、第１のバイポーラトランジスタと、上記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を上記第１のバイポーラトランジスタのベースと上記接続点とに出力する比較部とを具備するスイッチング回路である。これにより、カスコード接続された第１および第２のバイポーラトランジスタが一対の差動出力信号により制御されるという作用をもたらす。 The present technology has been made to solve the above-described problems. The first aspect of the present technology is a cascode connection between the first bipolar transistor and the first bipolar transistor at a connection point, and a threshold voltage is set. The second bipolar transistor to which a constant bias voltage not lower than the base is applied is compared with the input signal and a predetermined reference signal, and a pair of differential output signals indicating the comparison result are obtained from the first bipolar transistor. The switching circuit includes a base and a comparison unit that outputs to the connection point. As a result, the cascode-connected first and second bipolar transistors are controlled by a pair of differential output signals.
　また、この第１の側面において、上記比較部の入力段は、一対の差動トランジスタを備えてもよい。これにより、一対の差動トランジスタによって一対の差動出力信号が出力されるという作用をもたらす。 Also, in the first aspect, the input stage of the comparison unit may include a pair of differential transistors. Thereby, a pair of differential output signals are output by the pair of differential transistors.
　また、この第１の側面において、上記一対の差動トランジスタは、バイポーラトランジスタであってもよい。これにより、一対のバイポーラトランジスタによって一対の差動出力信号が出力されるという作用をもたらす。 In this first aspect, the pair of differential transistors may be bipolar transistors. As a result, a pair of differential output signals are output by the pair of bipolar transistors.
　また、この第１の側面において、上記一対の差動トランジスタは、ＭＯＳ(Metal Oxide Semiconductor)トランジスタであってもよい。これにより、一対のＭＯＳトランジスタによって一対の差動出力信号が出力されるという作用をもたらす。 In the first aspect, the pair of differential transistors may be MOS (Metal Oxide Semiconductor) transistors. As a result, a pair of differential output signals are output by the pair of MOS transistors.
　また、本技術の第２の側面は、第１のバイポーラトランジスタと、上記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を上記第１のバイポーラトランジスタのベースと上記接続点とに出力する比較部と、一定の電流を供給するリカバー電流源と、上記リカバー電流源と上記第２のバイポーラトランジスタとに接続されたコンデンサと、上記コンデンサの充放電電圧に応じてゲインを変化させる可変ゲインアンプとを具備する自動利得制御回路である。これにより、カスコード接続されたバイポーラトランジスタとリカバー電流源とに接続されたコンデンサの充放電電圧に応じてゲインが変化するという作用をもたらす。 In addition, according to a second aspect of the present technology, there is provided a first bipolar transistor and a second bias voltage that is cascode-connected to the first bipolar transistor at a connection point and a constant bias voltage not lower than a threshold voltage is applied to a base. A comparator that compares the bipolar transistor with an input signal and a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point; An automatic gain comprising: a recover current source for supplying a current; a capacitor connected to the recover current source and the second bipolar transistor; and a variable gain amplifier that changes a gain according to a charge / discharge voltage of the capacitor. It is a control circuit. As a result, the gain is changed according to the charge / discharge voltage of the capacitor connected to the cascode-connected bipolar transistor and the recovery current source.
　また、この第２の側面において、上記比較部の入力は、上記可変ゲインアンプの入力でも良い。 In this second aspect, the input of the comparison unit may be the input of the variable gain amplifier.
　また、この第２の側面において、上記比較部の入力は、上記可変ゲインアンプの出力でもよい。 In the second aspect, the input of the comparison unit may be the output of the variable gain amplifier.
　また、本技術の第３の側面は、入力信号と帰還信号との位相差および周波数差を検出して当該検出結果を示す第１および第２の出力信号を出力する検出器と、第１のバイポーラトランジスタと、上記第１のバイポーラトランジスタに第１の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、上記第１の出力信号と当該第１の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を上記第１のバイポーラトランジスタのベースと上記第１の接続点とに出力する第１の比較部と、第３のバイポーラトランジスタと、上記第３のバイポーラトランジスタに第２の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第４のバイポーラトランジスタと、上記第２の出力信号と当該第２の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を上記第３のバイポーラトランジスタのベースと上記第２の接続点とに出力する第２の比較部と、上記第２および第４のバイポーラトランジスタの接続点に接続されたコンデンサと、上記コンデンサの充放電圧に応じた周波数の周期信号を出力する電圧制御発振器と、上記周期信号を分周して上記帰還信号として上記検出器に帰還させる分周器とを具備する位相同期回路である。これにより、カスコード接続されたバイポーラトランジスタに接続されたコンデンサの充放電電圧に応じた周波数の周期信号が生成されるという作用をもたらす。 Further, a third aspect of the present technology includes a detector that detects a phase difference and a frequency difference between an input signal and a feedback signal and outputs first and second output signals indicating the detection result; A bipolar transistor, a second bipolar transistor that is cascode-connected to the first bipolar transistor at a first connection point, and to which a constant bias voltage not lower than a threshold voltage is applied to a base, and the first output signal, A first comparison for comparing a signal obtained by inverting the first output signal and outputting a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the first connection point , A third bipolar transistor, and a cascode connection to the third bipolar transistor at the second connection point, and a constant bias voltage not lower than the threshold voltage is applied to the base voltage. A pair of differential output signals indicating the comparison result by comparing the fourth bipolar transistor applied to the first output signal with the second output signal and a signal obtained by inverting the second output signal. A second comparator for outputting to the base of the transistor and the second connection point; a capacitor connected to the connection point of the second and fourth bipolar transistors; and a frequency corresponding to the charge / discharge voltage of the capacitor A phase controlled circuit comprising: a voltage-controlled oscillator that outputs a periodic signal; and a frequency divider that divides the periodic signal and feeds it back to the detector as the feedback signal. As a result, a periodic signal having a frequency corresponding to the charging / discharging voltage of the capacitor connected to the cascode-connected bipolar transistor is generated.
　本技術によれば、トランジスタを備えるＡＧＣ回路において、低域ノイズを低減しつつ、リーク電流を低減することができるという優れた効果を奏し得る。なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 According to the present technology, an AGC circuit including a transistor can have an excellent effect of reducing a leakage current while reducing low-frequency noise. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
本技術の第１の実施の形態における電流スイッチング回路の一構成例を示す回路図である。It is a circuit diagram showing an example of 1 composition of a current switching circuit in a 1st embodiment of this art. 本技術の第２の実施の形態における電子装置の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of an electronic device in a 2nd embodiment of this art. 本技術の第２の実施の形態におけるＡＧＣ回路の一構成例を示す回路図である。It is a circuit diagram showing an example of 1 composition of an AGC circuit in a 2nd embodiment of this art. 本技術の第２の実施の形態におけるピーク検波回路の一構成例を示す回路図である。It is a circuit diagram showing an example of 1 composition of a peak detection circuit in a 2nd embodiment of this art. 本技術の第２の実施の形態における入力電圧が参照電圧より高いときのスイッチング回路の状態の一例を示す図である。It is a figure showing an example of the state of a switching circuit when the input voltage in the 2nd embodiment of this art is higher than a reference voltage. 本技術の第２の実施の形態における入力電圧が参照電圧以下のときのスイッチング回路の状態の一例を示す図である。It is a figure showing an example of the state of a switching circuit when the input voltage in the 2nd embodiment of this art is below a reference voltage. 本技術の比較例におけるＡＧＣ回路の一構成例を示す回路図である。It is a circuit diagram showing an example of 1 composition of an AGC circuit in a comparative example of this art. 本技術の第２の実施の形態における入力電圧と出力電圧との変動の一例を示すタイミングチャートである。12 is a timing chart illustrating an example of fluctuations in input voltage and output voltage in the second embodiment of the present technology. 本技術の第２の実施の形態におけるＡＧＣ回路の動作の一例を示すタイミングチャートである。12 is a timing chart illustrating an example of the operation of the AGC circuit according to the second embodiment of the present technology. 本技術の第２の実施の形態におけるＡＧＣ回路の動作の一例を示すフローチャートである。12 is a flowchart illustrating an example of an operation of the AGC circuit according to the second embodiment of the present technology. 本技術の第２の実施の形態の変形例におけるＡＧＣ回路の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of an AGC circuit in a modification of a 2nd embodiment of this art. 本技術の第３の実施の形態における電子装置の一構成例を示すブロック図である。It is a block diagram showing an example of 1 composition of an electronic device in a 3rd embodiment of this art. 本技術の第３の実施の形態におけるチャージポンプの一構成例を示す回路図である。It is a circuit diagram showing an example of 1 composition of a charge pump in a 3rd embodiment of this art. 本技術の第３の実施の形態におけるチャージポンプの動作の一例を示すタイミングチャートである。12 is a timing chart illustrating an example of an operation of the charge pump according to the third embodiment of the present technology.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（電流スイッチング回路内のトランジスタをカスコード接続した例）
　２．第２の実施の形態（ＡＧＣ回路内のトランジスタをカスコード接続した例）
　３．第３の実施の形態（チャージポンプ内のトランジスタをカスコード接続した例）
　＜１．第１の実施の形態＞
　［電流スイッチング回路の構成例］ Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (example in which transistors in a current switching circuit are cascode-connected)
2. Second Embodiment (Example in which transistors in AGC circuit are cascode-connected)
3. Third embodiment (example in which transistors in a charge pump are cascode-connected)
<1. First Embodiment>
[Configuration example of current switching circuit]
　図１は、第１の実施の形態における電流スイッチング回路２４０の一構成例を示す回路図である。この電流スイッチング回路２４０は、比較部２５０と、バイポーラトランジスタ２４１および２４２とを備える。これらのバイポーラトランジスタ２４１および２４２は、例えば、ｎｐｎ型である。 FIG. 1 is a circuit diagram showing a configuration example of the current switching circuit 240 according to the first embodiment. The current switching circuit 240 includes a comparison unit 250 and bipolar transistors 241 and 242. These bipolar transistors 241 and 242 are, for example, npn type.
　バイポーラトランジスタ２４１のベースには、一定のバイアス電圧Ｖｂが印加される。このバイアス電圧Ｖｂは、例えば、バイポーラトランジスタ２４１の閾値電圧を下回らない値に設定される。 A constant bias voltage Vb is applied to the base of the bipolar transistor 241. For example, the bias voltage Vb is set to a value that does not fall below the threshold voltage of the bipolar transistor 241.
　バイポーラトランジスタ２４１のコレクタは、電流スイッチング回路２４０の出力端子に接続される。また、バイポーラトランジスタ２４１は、バイポーラトランジスタ２４２にカスコード接続される。なお、バイポーラトランジスタ２４２は、特許請求の範囲に記載の第１のトランジスタの一例である。また、バイポーラトランジスタ２４１は、特許請求の範囲に記載の第２のトランジスタの一例である。 The collector of the bipolar transistor 241 is connected to the output terminal of the current switching circuit 240. The bipolar transistor 241 is cascode-connected to the bipolar transistor 242. The bipolar transistor 242 is an example of a first transistor described in the claims. The bipolar transistor 241 is an example of a second transistor described in the claims.
　比較部２５０は、入力電圧Ｖｉｎと参照電圧Ｖｒｅｆとを比較するものである。この比較部は、比較結果を示す差動出力信号をバイポーラトランジスタ２４２のベースと、バイポーラトランジスタ２４１および２４２の接続点とに出力する。入力電圧Ｖｉｎの入力端子を正側入力端子とし、参照電圧Ｖｒｅｆの入力端子を負側入力端子とすると、正側の差動出力信号の出力電圧Ｖｏｐは、バイポーラトランジスタ２４２のベースに出力される。また、負側の差動出力信号の出力電圧Ｖｏｎは、バイポーラトランジスタ２４１および２４２の接続点に出力される。 The comparison unit 250 compares the input voltage Vin and the reference voltage Vref. The comparison unit outputs a differential output signal indicating the comparison result to the base of the bipolar transistor 242 and the connection point of the bipolar transistors 241 and 242. When the input terminal of the input voltage Vin is a positive input terminal and the input terminal of the reference voltage Vref is a negative input terminal, the output voltage Vop of the positive differential output signal is output to the base of the bipolar transistor 242. Further, the output voltage Von of the negative differential output signal is output to the connection point of the bipolar transistors 241 and 242.
　また、比較部２５０は、定電流源２６０と、スイッチ２７０および２８０と、バイポーラトランジスタ２５１および２５２とを備える。これらのバイポーラトランジスタ２５１および２５２は、例えば、ｎｐｎ型である。 The comparison unit 250 includes a constant current source 260, switches 270 and 280, and bipolar transistors 251 and 252. These bipolar transistors 251 and 252 are, for example, npn type.
　定電流源２６０は、一定の電流を供給するものである。スイッチ２７０は、参照電圧Ｖｒｅｆに対する入力電圧Ｖｉｎの値に応じて導通状態（すなわち、オン状態）および非導通状態（すなわち、オフ状態）のいずれかに移行するものである。例えば、入力電圧Ｖｉｎが参照電圧Ｖｒｅｆより高い場合にスイッチ２７０はオフ状態に移行する。スイッチ２８０は、スイッチ２７０と排他的に動作するものである。なお、スイッチ２７０および２８０は、特許請求の範囲に記載の一対の差動トランジスタの一例である。 The constant current source 260 supplies a constant current. The switch 270 shifts to either a conduction state (ie, an on state) or a non-conduction state (ie, an off state) according to the value of the input voltage Vin with respect to the reference voltage Vref. For example, when the input voltage Vin is higher than the reference voltage Vref, the switch 270 shifts to an off state. The switch 280 operates exclusively with the switch 270. The switches 270 and 280 are an example of a pair of differential transistors described in the claims.
　バイポーラトランジスタ２５１のエミッタは接地され、コレクタは、スイッチ２７０に接続される。また、バイポーラトランジスタ２５１のコレクタおよびベースは短絡（いわゆる、ダイオード接続）される。バイポーラトランジスタ２５１のベースは、バイポーラトランジスタ２４２のベースにも接続される。 The emitter of the bipolar transistor 251 is grounded, and the collector is connected to the switch 270. The collector and base of the bipolar transistor 251 are short-circuited (so-called diode connection). The base of the bipolar transistor 251 is also connected to the base of the bipolar transistor 242.
　バイポーラトランジスタ２５２のエミッタは接地され、コレクタは、スイッチ２８０に接続される。また、バイポーラトランジスタ２５２は、ダイオード接続されており、そのベースは、バイポーラトランジスタ２４１および２４２の接続点にも接続される。 The emitter of the bipolar transistor 252 is grounded, and the collector is connected to the switch 280. Bipolar transistor 252 is diode-connected, and its base is also connected to the connection point of bipolar transistors 241 and 242.
　上述の構成により、入力電圧Ｖｉｎが参照電圧Ｖｒｅｆより高い場合には、バイポーラトランジスタ２４１および２４２がオフ状態となる。一方、入力電圧Ｖｉｎが参照電圧Ｖｒｅｆ以下の場合には、バイポーラトランジスタ２４１および２４２がオン状態となる。バイポーラトランジスタ２４１および２４２は、カスコード接続されているため、電流スイッチング回路２４０の出力端子から見た出力抵抗は、バイポーラトランジスタ１つのみでスイッチングする際の比較例より高くなる。これにより、リーク電流を小さくすることができる。また、バイポーラトランジスタ２４１および２４２によりスイッチングするため、ＭＯＳトランジスタを用いる場合と比較して１／ｆノイズを低減することができる。 With the above configuration, when the input voltage Vin is higher than the reference voltage Vref, the bipolar transistors 241 and 242 are turned off. On the other hand, when the input voltage Vin is equal to or lower than the reference voltage Vref, the bipolar transistors 241 and 242 are turned on. Since the bipolar transistors 241 and 242 are cascode-connected, the output resistance viewed from the output terminal of the current switching circuit 240 is higher than that in the comparative example when switching is performed with only one bipolar transistor. Thereby, the leakage current can be reduced. Further, since switching is performed by the bipolar transistors 241 and 242, the 1 / f noise can be reduced as compared with the case where the MOS transistor is used.
　このように、本技術の第１の実施の形態によれば、比較部２５０によりオンオフされる２つのバイポーラトランジスタがカスコード接続されているため、トランジスタが１つのみの場合よりも出力抵抗が高くなる。これにより、それらのトランジスタのリーク電流を少なくすることができる。 As described above, according to the first embodiment of the present technology, since the two bipolar transistors that are turned on / off by the comparison unit 250 are cascode-connected, the output resistance is higher than when only one transistor is used. . Thereby, the leakage current of those transistors can be reduced.
　＜２．第２の実施の形態＞
　［電子装置の構成例］
　図２は、第２の実施の形態における電子装置１００の一構成例を示すブロック図である。この電子装置１００は、アナログ信号を処理する装置であり、アナログ信号出力部１１０、ＡＧＣ回路２００および信号処理部１２０を備える。電子装置１００としては、例えば、無線通信装置、音響装置や映像再生装置などが想定される。 <2. Second Embodiment>
[Configuration example of electronic device]
FIG. 2 is a block diagram illustrating a configuration example of the electronic device 100 according to the second embodiment. The electronic device 100 is a device that processes an analog signal, and includes an analog signal output unit 110, an AGC circuit 200, and a signal processing unit 120. As the electronic device 100, for example, a wireless communication device, an audio device, a video reproduction device, or the like is assumed.
　アナログ信号出力部１１０は、入力電圧Ｖｉｎのアナログ信号をＡＧＣ回路２００に信号線１１９を介して出力するものである。アナログ信号出力部１１０として、例えば、無線通信装置におけるアンテナや、センサー（イメージセンサーやマイクなど）が想定される。 The analog signal output unit 110 outputs an analog signal of the input voltage Vin to the AGC circuit 200 via the signal line 119. As the analog signal output unit 110, for example, an antenna or a sensor (such as an image sensor or a microphone) in a wireless communication device is assumed.
　ＡＧＣ回路２００は、アナログ信号の振幅に応じたゲインにより、その信号の入力電圧Ｖｉｎを増減するものである。このＡＧＣ回路２００は、振幅調整した電圧を出力電圧Ｖｏｕｔとして信号処理部１２０に信号線２０９を介して供給する。なお、ＡＧＣ回路２００は、特許請求の範囲に記載の自動利得制御回路の一例である。 The AGC circuit 200 increases or decreases the input voltage Vin of the signal by a gain corresponding to the amplitude of the analog signal. The AGC circuit 200 supplies the voltage whose amplitude has been adjusted to the signal processing unit 120 via the signal line 209 as the output voltage Vout. The AGC circuit 200 is an example of an automatic gain control circuit described in the claims.
　信号処理部１２０は、出力電圧Ｖｏｕｔのアナログ信号に対して所定の処理を行うものである。この信号処理部１２０は、例えば、ＡＤ変換処理や、無線信号を復号する復号処理などを実行する。 The signal processing unit 120 performs predetermined processing on the analog signal of the output voltage Vout. The signal processing unit 120 executes, for example, AD conversion processing, decoding processing for decoding a radio signal, and the like.
　［ＡＧＣ回路の構成例］
　図３は、第２の実施の形態におけるＡＧＣ回路２００の一構成例を示す回路図である。このＡＧＣ回路２００は、可変ゲインアンプ２１０およびピーク検波回路２２０を備える。また、ピーク検波回路２２０は、参照電圧供給部２２１、コンデンサ２２２、バイアス電圧供給部２３０および電流スイッチング回路２４０を備える。電流スイッチング回路２４０の構成は、一定の電流を供給するリカバー電流源２９０が追加されている点以外は、第１の実施の形態と同様である。このリカバー電流源２９０は、バイポーラトランジスタ２４１および出力端子に接続される。 [Configuration example of AGC circuit]
FIG. 3 is a circuit diagram showing a configuration example of the AGC circuit 200 according to the second embodiment. The AGC circuit 200 includes a variable gain amplifier 210 and a peak detection circuit 220. The peak detection circuit 220 includes a reference voltage supply unit 221, a capacitor 222, a bias voltage supply unit 230, and a current switching circuit 240. The configuration of the current switching circuit 240 is the same as that of the first embodiment except that a recover current source 290 that supplies a constant current is added. This recovering current source 290 is connected to the bipolar transistor 241 and the output terminal.
　参照電圧供給源２２１は、所望の出力信号Ｖｏｕｔの振幅を得るために、入力電圧信号Vinの下限の閾値レベルを比較部２５０に供給するものである。バイアス電圧供給部２３０は、一定のバイアス電圧Ｖｂを電流スイッチング回路２４０に供給するものである。 The reference voltage supply source 221 supplies a lower limit threshold level of the input voltage signal Vin to the comparison unit 250 in order to obtain a desired amplitude of the output signal Vout. The bias voltage supply unit 230 supplies a constant bias voltage Vb to the current switching circuit 240.
　コンデンサ２２２の一端は、電流スイッチング回路２４０の出力端子と可変ゲインアンプ２１０とに接続される。このコンデンサ２２２は、電流スイッチング回路２４０の出力端子からの制御電流Ｉｃｏｎを充放電して制御電圧Ｖｃを生成する。 One end of the capacitor 222 is connected to the output terminal of the current switching circuit 240 and the variable gain amplifier 210. The capacitor 222 charges and discharges the control current Icon from the output terminal of the current switching circuit 240 to generate the control voltage Vc.
　可変ゲインアンプ２１０は、制御電圧Ｖｃに応じてゲインを変化させるものである。例えば、制御電圧Ｖｃが高いほど、ゲインが大きくなる。この可変ゲインアンプ２１０は、制御電圧Ｖｃに応じたゲインで入力電圧Ｖｉｎを増減し、増減した電圧を出力電圧Ｖｏｕｔとして信号処理部１２０に出力する。 The variable gain amplifier 210 changes the gain according to the control voltage Vc. For example, the higher the control voltage Vc, the larger the gain. The variable gain amplifier 210 increases or decreases the input voltage Vin with a gain corresponding to the control voltage Vc, and outputs the increased or decreased voltage to the signal processing unit 120 as the output voltage Vout.
　［ピーク検波回路の構成例］
　図４は、第２の実施の形態におけるピーク検波回路２２０の一構成例を示す回路図である。ピーク検波回路２２０において、定電流源２６０は、例えば、バイポーラトランジスタ２６１および２６２を備える。また、スイッチ２７０として、バイポーラトランジスタ２７１が用いられ、スイッチ２８０としてバイポーラトランジスタ２８１が用いられる。また、バイアス電圧供給部２３０は、バイポーラトランジスタ２３１および２３３と、抵抗２３２とを備える。リカバー電流源２９０は、ＭＯＳ(Metal Oxide Semiconductor)トランジスタ２９１を備える。 [Configuration example of peak detection circuit]
FIG. 4 is a circuit diagram showing a configuration example of the peak detection circuit 220 according to the second embodiment. In the peak detection circuit 220, the constant current source 260 includes, for example, bipolar transistors 261 and 262. Further, a bipolar transistor 271 is used as the switch 270, and a bipolar transistor 281 is used as the switch 280. The bias voltage supply unit 230 includes bipolar transistors 231 and 233 and a resistor 232. The recovering current source 290 includes a MOS (Metal Oxide Semiconductor) transistor 291.
　バイポーラトランジスタ２３１、２６１、２６２、２７１および２８１は、例えば、ｐｎｐ型であり、バイポーラトランジスタ２３３は、例えば、ｎｐｎ型である。また、ＭＯＳトランジスタ２９１は、例えば、Ｐ型である。 The bipolar transistors 231, 261, 262, 271 and 281 are, for example, pnp type, and the bipolar transistor 233 is, for example, npn type. The MOS transistor 291 is, for example, P type.
　バイポーラトランジスタ２６１のエミッタは電源に接続され、ベースはバイポーラトランジスタ２６２および２３１のベースに接続される。また、バイポーラトランジスタ２６１は、ダイオード接続されており、そのコレクタは、参照電流Ｉｒｅｆを供給する定電流源（不図示）に接続される。 The emitter of the bipolar transistor 261 is connected to the power supply, and the base is connected to the bases of the bipolar transistors 262 and 231. The bipolar transistor 261 is diode-connected, and its collector is connected to a constant current source (not shown) that supplies a reference current Iref.
　バイポーラトランジスタ２６２のエミッタは電源に接続され、コレクタは、バイポーラトランジスタ２７１および２８１のエミッタに接続される。このようなカレントミラー回路により、参照電流Ｉｒｅｆが複製される。 The emitter of the bipolar transistor 262 is connected to the power supply, and the collector is connected to the emitters of the bipolar transistors 271 and 281. The reference current Iref is duplicated by such a current mirror circuit.
　バイポーラトランジスタ２７１のベースには、入力電圧Ｖｉｎが入力され、コレクタはバイポーラトランジスタ２５１に接続される。バイポーラトランジスタ２８１のベースには、参照電圧Ｖｒｅｆが入力され、コレクタはバイポーラトランジスタ２５２に接続される。 The input voltage Vin is input to the base of the bipolar transistor 271, and the collector is connected to the bipolar transistor 251. The reference voltage Vref is input to the base of the bipolar transistor 281, and the collector is connected to the bipolar transistor 252.
　バイポーラトランジスタ２３１のエミッタは電源に接続され、コレクタは、抵抗２３２とバイポーラトランジスタ２４１のベースとに接続される。また、バイポーラトランジスタ２３３は、ダイオード接続され、抵抗２３２と接地端子との間に挿入される。バイポーラトランジスタ２３１により、参照電流Ｉｒｅｆを複製した電流が生成され、その電流と抵抗２３２およびバイポーラトランジスタ２３３とにより、バイアス電圧Ｖｂが生成される。 The emitter of the bipolar transistor 231 is connected to the power supply, and the collector is connected to the resistor 232 and the base of the bipolar transistor 241. The bipolar transistor 233 is diode-connected and is inserted between the resistor 232 and the ground terminal. The bipolar transistor 231 generates a current that duplicates the reference current Iref, and the current, the resistor 232, and the bipolar transistor 233 generate a bias voltage Vb.
　ＭＯＳトランジスタ２９１はダイオード接続され、そのドレインがバイポーラトランジスタ２４１とコンデンサ２２２とに接続される。 The MOS transistor 291 is diode-connected, and its drain is connected to the bipolar transistor 241 and the capacitor 222.
　上述したように、参照電流Ｉｒｅｆを複製した電流を用いて比較部２５０が出力電圧ＶｏｐおよびＶｏｎを生成する。同様に、参照電流Ｉｒｅｆを複製した電流を用いてバイアス電圧供給部２３０が、バイアス電圧Ｖｂを生成する。このため、プロセス、電圧や温度などの条件（ＰＶＴ条件）により参照電流Ｉｒｅｆにばらつきが生じても、その電流に応じてバイアス電圧Ｖｂ、出力電圧ＶｏｐおよびＶｏｎが同程度に増減する。 As described above, the comparison unit 250 generates the output voltages Vop and Von using a current that is a copy of the reference current Iref. Similarly, the bias voltage supply unit 230 generates the bias voltage Vb using a current that is a copy of the reference current Iref. For this reason, even if the reference current Iref varies depending on conditions such as process, voltage, and temperature (PVT conditions), the bias voltage Vb, the output voltages Vop, and Von increase or decrease to the same extent according to the current.
　図５は、第２の実施の形態における入力電圧Ｖｉｎが参照電圧Ｖｒｅｆより高いときの電流スイッチング回路２４０の状態の一例を示す図である。スイッチ２７０およびバイポーラトランジスタ２５１に流れる電流が減少し、スイッチ２８０およびバイポーラトランジスタ２５２に流れる電流が増大する。これにより、バイポーラトランジスタ２４２のベース電位（Ｖｏｐ）が低下し、バイポーラトランジスタ２４１のエミッタ電位（Ｖｏｎ）が上昇する。 FIG. 5 is a diagram illustrating an example of the state of the current switching circuit 240 when the input voltage Vin is higher than the reference voltage Vref in the second embodiment. The current flowing through switch 270 and bipolar transistor 251 decreases, and the current flowing through switch 280 and bipolar transistor 252 increases. As a result, the base potential (Vop) of the bipolar transistor 242 decreases, and the emitter potential (Von) of the bipolar transistor 241 increases.
　ベース電位の低下によりバイポーラトランジスタ２４２はオフ状態に移行する。また、バイポーラトランジスタ２４１のベースにバイアス電圧Ｖｂが印加されているため、バイポーラトランジスタ２４１のベース－エミッタ間電圧は閾値電圧未満となる。このため、バイポーラトランジスタ２４１もオフ状態に移行する。 The bipolar transistor 242 shifts to an off state due to a decrease in base potential. Further, since the bias voltage Vb is applied to the base of the bipolar transistor 241, the base-emitter voltage of the bipolar transistor 241 becomes less than the threshold voltage. For this reason, the bipolar transistor 241 is also turned off.
　バイポーラトランジスタ２４１および２４２がオフ状態であるため、リカバー電流源２９０の電流Ｉｒが、ほとんどそのまま制御電流Ｉｃｏｎとして出力され、その電流によりコンデンサ２２２が充放電される。この結果、制御電圧Ｖｃが時間の経過に伴って上昇する Since the bipolar transistors 241 and 242 are in the off state, the current Ir of the recover current source 290 is almost output as the control current Icon, and the capacitor 222 is charged / discharged by the current. As a result, the control voltage Vc increases with time.
　図６は、第２の実施の形態における入力電圧Ｖｉｎが参照電圧Ｖｒｅｆ以下のときの電流スイッチング回路２４０の状態の一例を示す図である。スイッチ２７０およびバイポーラトランジスタ２５１に流れる電流が増大し、スイッチ２８０およびバイポーラトランジスタ２５２に流れる電流が減少する。これにより、バイポーラトランジスタ２４２のベース電位（Ｖｏｐ）が上昇し、バイポーラトランジスタ２４１のエミッタ電位（Ｖｏｎ）が低下する。 FIG. 6 is a diagram illustrating an example of the state of the current switching circuit 240 when the input voltage Vin is equal to or lower than the reference voltage Vref in the second embodiment. The current flowing through switch 270 and bipolar transistor 251 increases, and the current flowing through switch 280 and bipolar transistor 252 decreases. As a result, the base potential (Vop) of the bipolar transistor 242 increases, and the emitter potential (Von) of the bipolar transistor 241 decreases.
　ベース電位の上昇によりバイポーラトランジスタ２４２はオン状態に移行する。また、バイポーラトランジスタ２４１のベースにバイアス電圧Ｖｂが印加されているため、バイポーラトランジスタ２４１のベース－エミッタ間電圧は閾値電圧以上となる。このため、バイポーラトランジスタ２４１もオン状態に移行する。 The bipolar transistor 242 shifts to the on state due to the rise of the base potential. Further, since the bias voltage Vb is applied to the base of the bipolar transistor 241, the base-emitter voltage of the bipolar transistor 241 becomes equal to or higher than the threshold voltage. For this reason, the bipolar transistor 241 is also turned on.
　オン状態のバイポーラトランジスタ２４１および２４２に流れるアタック電流Ｉａによりコンデンサ２２２の蓄積電荷が引き抜かれ、制御電圧Ｖｃが時間の経過に伴って低下する。 The accumulated charge of the capacitor 222 is extracted by the attack current Ia flowing through the bipolar transistors 241 and 242 in the on state, and the control voltage Vc decreases with time.
　図７は、比較例におけるＡＧＣ回路の一構成例を示す回路図である。この比較例では、比較部の出力によりオンオフするトランジスタが１つのみ設けられる。ここで、ＡＧＣ回路の時定数Ｔｂは、一般に、トランジスタからの制御電流をＩｃｏｎとし、コンデンサの容量をＣとすると、次の式により表される。
　Ｔｃ＝Ｃ／Ｉｃｏｎ FIG. 7 is a circuit diagram showing a configuration example of the AGC circuit in the comparative example. In this comparative example, only one transistor that is turned on / off by the output of the comparison unit is provided. Here, the time constant Tb of the AGC circuit is generally expressed by the following expression, where Icon is the control current from the transistor and C is the capacitance of the capacitor.
Tc = C / Icon
　比較例において、時定数Ｔｃを大きくするには、上式より制御電流Ｉｃｏｎを小さくするか、容量Ｃを大きくすればよい。容量Ｃを大きくすると、コンデンサのサイズが増大し、回路のレイアウト面積が広くなってしまう。容量Ｃを増大せずに時定数Ｔｃを大きくするには、制御電流Ｉｃｏｎを小さくすればよい。ところが、制御電流Ｉｃｏｎを小さくすると、トランジスタがオフ状態の際に流れるリーク電流が相対的に大きくなるおそれがある。そして、そのリーク電流の増大により、コンデンサから電流を引き抜くためのアタック電流Ｉａが所望値より少なくなり、ＡＧＣ回路の動作点が設計値と異なる値となってしまう。 In the comparative example, in order to increase the time constant Tc, the control current Icon may be reduced or the capacitance C may be increased from the above equation. Increasing the capacitance C increases the size of the capacitor and increases the circuit layout area. In order to increase the time constant Tc without increasing the capacitance C, the control current Icon may be decreased. However, when the control current Icon is reduced, the leakage current that flows when the transistor is off may be relatively increased. As the leakage current increases, the attack current Ia for extracting the current from the capacitor becomes smaller than a desired value, and the operating point of the AGC circuit becomes a value different from the design value.
　これに対して、電流スイッチング回路２４０では、比較部２５０の出力段にカスコード接続されたバイポーラトランジスタ２４１および２４２を設けている。電流スイッチング回路２４０の出力端子から見た出力抵抗は、バイポーラトランジスタ１つのみでスイッチングする際の比較例より高くなる。これにより、比較例よりもリーク電流を小さくすることができる。また、バイポーラトランジスタ２４１および２４２によりスイッチングするため、ＭＯＳトランジスタを用いる場合と比較して１／ｆノイズを低減することができる。 On the other hand, in the current switching circuit 240, bipolar transistors 241 and 242 connected in cascode are provided at the output stage of the comparison unit 250. The output resistance viewed from the output terminal of the current switching circuit 240 is higher than that in the comparative example when switching is performed with only one bipolar transistor. Thereby, the leakage current can be made smaller than that of the comparative example. Further, since switching is performed by the bipolar transistors 241 and 242, the 1 / f noise can be reduced as compared with the case where the MOS transistor is used.
　なお、ＡＧＣ回路２００内のトランジスタは、１／ｆノイズを低減する観点から、バイポーラトランジスタとすることが望ましいが、一部をＭＯＳトランジスタとすることもできる。 The transistors in the AGC circuit 200 are preferably bipolar transistors from the viewpoint of reducing 1 / f noise, but some of them may be MOS transistors.
　［ＡＧＣ回路の動作例］
　図８は、第２の実施の形態における入力電圧Ｖｉｎと出力電圧Ｖｏｕｔとの変動の一例を示すタイミングチャートである。同図に例示するように、時刻Ｔ１から時刻Ｔ２までの間において、入力電圧Ｖｉｎの振幅が低下したものとする。この場合にＡＧＣ回路２００は、比較的大きなゲインにより入力電圧Ｖｉｎを増減して出力電圧Ｖｏｕｔとして出力する。そして、時刻Ｔ２以降において、入力電圧Ｖｉｎの振幅が上昇したものとする。この場合にＡＧＣ回路２００は、比較的小さなゲインにより入力電圧Ｖｉｎを増減して出力電圧Ｖｏｕｔとして出力する。このような制御により、出力電圧Ｖｏｕｔの振幅を一定にすることができる。 [Operation example of AGC circuit]
FIG. 8 is a timing chart showing an example of fluctuations in the input voltage Vin and the output voltage Vout in the second embodiment. As illustrated in the figure, it is assumed that the amplitude of the input voltage Vin decreases between time T1 and time T2. In this case, the AGC circuit 200 increases / decreases the input voltage Vin with a relatively large gain and outputs it as the output voltage Vout. Then, it is assumed that the amplitude of the input voltage Vin has increased after time T2. In this case, the AGC circuit 200 increases / decreases the input voltage Vin with a relatively small gain and outputs it as the output voltage Vout. By such control, the amplitude of the output voltage Vout can be made constant.
　図９は、第２の実施の形態におけるＡＧＣ回路２００の動作の一例を示すタイミングチャートである。時刻ｔ０から時刻ｔ１までの期間において、入力電圧Ｖｉｎは、参照電圧Ｖｒｅｆより高くなる。この期間においてＡＧＣ回路２００は、リカバー電流源からの電流Ｉｒによりコンデンサ２２２を充放電し、制御電圧Ｖｃが時間の経過に伴って上昇する。 FIG. 9 is a timing chart showing an example of the operation of the AGC circuit 200 according to the second embodiment. In the period from time t0 to time t1, the input voltage Vin is higher than the reference voltage Vref. During this period, the AGC circuit 200 charges and discharges the capacitor 222 with the current Ir from the recovering current source, and the control voltage Vc increases with time.
　時刻ｔ１から時刻ｔ２までの期間において入力電圧Ｖｉｎは、参照電圧Ｖｒｅｆ以下である。この期間においてＡＧＣ回路２００は、コンデンサ２２２をアタック電流Ｉａにより放電し、制御電圧Ｖｃが時間の経過に伴って低下する。 During the period from time t1 to time t2, the input voltage Vin is equal to or lower than the reference voltage Vref. During this period, the AGC circuit 200 discharges the capacitor 222 with the attack current Ia, and the control voltage Vc decreases with time.
　また、時刻ｔ２から時刻ｔ３までの期間において、入力電圧Ｖｉｎは、参照電圧Ｖｒｅｆより高くなり、制御電圧Ｖｃが時間の経過に伴って上昇する。 In the period from time t2 to time t3, the input voltage Vin becomes higher than the reference voltage Vref, and the control voltage Vc rises with time.
　時刻ｔ０からｔ３までの期間を、入力電圧Ｖｉｎの周期Ｐとし、時刻ｔ１からｔ２までの期間をＰ１とすると、上述の動作の繰り返しにより次の式が成立する。
　　Ｉｒ×Ｐ＝Ｉａ×Ｐ１ Assuming that the period from time t0 to t3 is the period P of the input voltage Vin and the period from time t1 to t2 is P1, the following equation is established by repeating the above operation.
Ir × P = Ia × P1
　上式の右辺または左辺により表される電流の積分値に応じた制御電圧Ｖｃが、コンデンサ２２２により生成される。リーク電流を小さく出来れば、制御電流Ｉｃｏｎを小さくすることが出来、小さな容量Ｃでも大きな時定数Ｔｃを実現可能である。 The control voltage Vc corresponding to the integrated value of the current represented by the right side or the left side of the above equation is generated by the capacitor 222. If the leakage current can be reduced, the control current Icon can be reduced, and a large time constant Tc can be realized with a small capacitance C.
　図１０は、第２の実施の形態におけるＡＧＣ回路２００の動作の一例を示すフローチャートである。この動作は、例えば、ＡＧＣ回路２００にアナログ信号が入力されたときに開始する。 FIG. 10 is a flowchart showing an example of the operation of the AGC circuit 200 according to the second embodiment. This operation starts, for example, when an analog signal is input to the AGC circuit 200.
　ＡＧＣ回路２００は、入力電圧Ｖｉｎが参照電圧Ｖｒｅｆより高いか否かを判断する（ステップＳ９０１）。入力電圧Ｖｉｎが参照電圧Ｖｒｅｆ以下の場合に（ステップＳ９０１：Ｎｏ）、ＡＧＣ回路２００は、制御電圧Ｖｃを徐々に低下させる（ステップＳ９０２）。制御電圧Ｖｃの低下に応じてゲインは小さくなる。 The AGC circuit 200 determines whether or not the input voltage Vin is higher than the reference voltage Vref (step S901). When the input voltage Vin is equal to or lower than the reference voltage Vref (step S901: No), the AGC circuit 200 gradually decreases the control voltage Vc (step S902). The gain decreases as the control voltage Vc decreases.
　一方、入力電圧Ｖｉｎが参照電圧Ｖｒｅｆより高い場合に（ステップＳ９０１：Ｙｅｓ）、ＡＧＣ回路２００は、制御電圧Ｖｃを徐々に上昇させる（ステップＳ９０３）。制御電圧Ｖｃの上昇に応じてゲインは大きくなる。ステップＳ９０２またはＳ９０３の後に、ＡＧＣ回路２００は、そのゲインにより入力電圧Ｖｉｎを増減する（ステップＳ９０４）。 On the other hand, when the input voltage Vin is higher than the reference voltage Vref (step S901: Yes), the AGC circuit 200 gradually increases the control voltage Vc (step S903). The gain increases as the control voltage Vc increases. After step S902 or S903, the AGC circuit 200 increases or decreases the input voltage Vin according to the gain (step S904).
　このように、本技術の第２の実施の形態によれば、比較部２５０によりオンオフされる２つのバイポーラトランジスタがカスコード接続されているため、トランジスタが１つのみの場合よりも出力抵抗が高くなる。これにより、それらのトランジスタのリーク電流を少なくすることができる。 As described above, according to the second embodiment of the present technology, the two bipolar transistors that are turned on / off by the comparison unit 250 are cascode-connected, so that the output resistance is higher than when only one transistor is used. . Thereby, the leakage current of those transistors can be reduced.
　［変形例］
　上述の第２の実施の形態では、ピーク検波回路２２０は、増減前の入力電圧Ｖｉｎから制御電圧Ｖｃを生成するフィードフォワード制御を行っていたが、フィードバック制御でも実現できる。 [Modification]
In the second embodiment described above, the peak detection circuit 220 performs the feedforward control for generating the control voltage Vc from the input voltage Vin before increase / decrease, but can also be realized by feedback control.
　図１１は、第２の実施の形態の変形例におけるＡＧＣ回路２００の一構成例を示すブロック図である。このＡＧＣ回路２００において、可変ゲインアンプ２１０は、出力電圧Ｖｏｕｔをピーク検波回路２２０に入力する（言い換えれば、帰還させる）。そして、ピーク検波回路２２０は、出力電圧Ｖｏｕｔと参照電圧Ｖｒｅｆとを比較して制御電圧Ｖｃを生成する。 FIG. 11 is a block diagram illustrating a configuration example of the AGC circuit 200 according to a modification of the second embodiment. In the AGC circuit 200, the variable gain amplifier 210 inputs (in other words, feeds back) the output voltage Vout to the peak detection circuit 220. Then, the peak detection circuit 220 compares the output voltage Vout with the reference voltage Vref and generates a control voltage Vc.
　このように本技術の第２の実施の形態の変形例によれば、可変ゲインアンプ２１０が出力電圧Ｖｏｕｔをピーク検波回路２２０に帰還させるため、フィードバック制御を行うことができる。 As described above, according to the modification of the second embodiment of the present technology, the variable gain amplifier 210 feeds back the output voltage Vout to the peak detection circuit 220, so that feedback control can be performed.
　＜３．第３の実施の形態＞
　上述の第１の実施の形態では、カスコード接続のトランジスタをＡＧＣ回路２００に設けていたが、スイッチング動作を行う回路であれば、チャージポンプなど、ＡＧＣ回路２００以外の回路にカスコード接続のトランジスタを設けることもできる。この第２の実施の形態の電子装置は、チャージポンプにカスコード接続のトランジスタを設けた点において第１の実施の形態と異なる。 <3. Third Embodiment>
In the first embodiment described above, the cascode-connected transistor is provided in the AGC circuit 200. However, if the circuit performs a switching operation, a cascode-connected transistor is provided in a circuit other than the AGC circuit 200 such as a charge pump. You can also. The electronic device according to the second embodiment is different from the first embodiment in that a cascode-connected transistor is provided in the charge pump.
　図１２は、第３の実施の形態における電子装置１０１の一構成例を示すブロック図である。この電子装置１０１は、位相同期回路１３０および信号処理部１４０を備える。 FIG. 12 is a block diagram illustrating a configuration example of the electronic device 101 according to the third embodiment. The electronic device 101 includes a phase synchronization circuit 130 and a signal processing unit 140.
　位相同期回路１３０は、位相雑音の低い外部クロックＣＬＫｉｎを基準信号として電圧制御発振器の発振周波数を安定化させる目的で利用される。クロック信号ＣＬＫｉｎは、水晶発振器などにより生成される。この位相同期回路１３０は、位相／周波数検出器１３１、チャージポンプ３００、電圧制御発振器１３２および分周器１３３を備える。 The phase synchronization circuit 130 is used for the purpose of stabilizing the oscillation frequency of the voltage controlled oscillator using the external clock CLKin having a low phase noise as a reference signal. The clock signal CLKin is generated by a crystal oscillator or the like. The phase synchronization circuit 130 includes a phase / frequency detector 131, a charge pump 300, a voltage controlled oscillator 132, and a frequency divider 133.
　位相／周波数検出器１３１は、クロック信号ＣＬＫｉｎと、分周器１３３から帰還したクロック信号ＣＬＫｆｂとの位相差および周波数差を検出するものである。この位相／周波数検出器１３１は、検出結果を示す出力信号ＶｏａおよびＶｏｂをチャージポンプ３００に供給する。なお、位相／周波数検出器１３１は、特許請求の範囲に記載の検出器の一例である。 The phase / frequency detector 131 detects a phase difference and a frequency difference between the clock signal CLKin and the clock signal CLKfb fed back from the frequency divider 133. The phase / frequency detector 131 supplies output signals Voa and Vob indicating the detection result to the charge pump 300. The phase / frequency detector 131 is an example of the detector described in the claims.
　チャージポンプ３００は、位相差および周波数差に応じた制御電圧Ｖｃを生成するものである。このチャージポンプ３００は、制御電圧Ｖｃを電圧制御発振器１３２に供給する。 The charge pump 300 generates the control voltage Vc according to the phase difference and the frequency difference. The charge pump 300 supplies the control voltage Vc to the voltage controlled oscillator 132.
　電圧制御発振器１３２は、制御電圧Ｖｃに応じた周波数の信号を周期信号ＶＣＯｏｕｔとして生成するものである。この電圧制御発振器１３２は、周期信号ＶＣＯｏｕｔを信号処理部１４０および分周器１３３に供給する。 The voltage controlled oscillator 132 generates a signal having a frequency corresponding to the control voltage Vc as the periodic signal VCOout. The voltage controlled oscillator 132 supplies the periodic signal VCOout to the signal processing unit 140 and the frequency divider 133.
　分周器１３３は、所定の分周比により周期信号ＶＣＯｏｕｔを分周するものである。この分周器１３３は、分周した信号をクロック信号ＣＬＫｆｂとして位相／周波数検出器１３１に帰還させる。 The frequency divider 133 divides the periodic signal VCOout by a predetermined frequency division ratio. The frequency divider 133 feeds back the frequency-divided signal to the phase / frequency detector 131 as the clock signal CLKfb.
　信号処理部１４０は、周期信号ＶＣＯｏｕｔに同期して、所定の信号処理を実行するものである。 The signal processing unit 140 performs predetermined signal processing in synchronization with the periodic signal VCOout.
　図１３は、第３の実施の形態におけるチャージポンプ３００の一構成例を示す回路図である。このチャージポンプ３００は、インバータ３１０および３１１と、定電流源３２１および３３５と、バイポーラトランジスタ３２２乃至３２５と、バイポーラトランジスタ３３１乃至３３４とを備える。また、チャージポンプ３００は、バイポーラトランジスタ３４１乃至３４４と、コンデンサ３５０とを備える。 FIG. 13 is a circuit diagram showing a configuration example of the charge pump 300 according to the third embodiment. The charge pump 300 includes inverters 310 and 311, constant current sources 321 and 335, bipolar transistors 322 to 325, and bipolar transistors 331 to 334. The charge pump 300 includes bipolar transistors 341 to 344 and a capacitor 350.
　バイポーラトランジスタ３２２、３２４、３３１、３３３、３４１、３４２は、例えば、ｐｎｐ型であり、バイポーラトランジスタ３２３、３２５、３３２、３３４、３４３および３４４は、例えば、ｎｐｎ型である。 The bipolar transistors 322, 324, 331, 333, 341, and 342 are, for example, pnp type, and the bipolar transistors 323, 325, 332, 334, 343, and 344 are, for example, npn type.
　バイポーラトランジスタ３２２および３２４のエミッタは、定電流源３２１に接続される。また、バイポーラトランジスタ３２２のベースは、インバータ３１０の出力端子に接続され、バイポーラトランジスタ３２４のベースには、出力信号Ｖｏｂが入力される。バイポーラトランジスタ３２２のコレクタは、バイポーラトランジスタ３２３のコレクタに接続され、バイポーラトランジスタ３２４のコレクタは、バイポーラトランジスタ３２５のコレクタに接続される。インバータ３１０は、出力信号Ｖｏｂを反転する。 The emitters of the bipolar transistors 322 and 324 are connected to the constant current source 321. The base of the bipolar transistor 322 is connected to the output terminal of the inverter 310, and the output signal Vob is input to the base of the bipolar transistor 324. The collector of bipolar transistor 322 is connected to the collector of bipolar transistor 323, and the collector of bipolar transistor 324 is connected to the collector of bipolar transistor 325. Inverter 310 inverts output signal Vob.
　また、バイポーラトランジスタ３２３のコレクタは、バイポーラトランジスタ３２３自身のベースと、バイポーラトランジスタ３４４のベースとに接続される。バイポーラトランジスタ３２５のコレクタは、バイポーラトランジスタ３２５自身のベースと、バイポーラトランジスタ３４３および３４４の接続点とに接続される。バイポーラトランジスタ３２３および３２５のエミッタは接地される。 Also, the collector of the bipolar transistor 323 is connected to the base of the bipolar transistor 323 itself and the base of the bipolar transistor 344. The collector of the bipolar transistor 325 is connected to the base of the bipolar transistor 325 itself and the connection point of the bipolar transistors 343 and 344. The emitters of bipolar transistors 323 and 325 are grounded.
　バイポーラトランジスタ３３２および３３４のエミッタは、定電流源３３５に接続される。また、バイポーラトランジスタ３３２のベースは、インバータ３１１の出力端子に接続され、バイポーラトランジスタ３３４のベースには、出力信号Ｖｏａが入力される。バイポーラトランジスタ３３２のコレクタは、バイポーラトランジスタ３３１のコレクタに接続され、バイポーラトランジスタ３３４のコレクタは、バイポーラトランジスタ３３３のコレクタに接続される。インバータ３１１は、出力信号Ｖｏａを反転する。 The emitters of the bipolar transistors 332 and 334 are connected to a constant current source 335. The base of the bipolar transistor 332 is connected to the output terminal of the inverter 311, and the output signal Voa is input to the base of the bipolar transistor 334. The collector of bipolar transistor 332 is connected to the collector of bipolar transistor 331, and the collector of bipolar transistor 334 is connected to the collector of bipolar transistor 333. The inverter 311 inverts the output signal Voa.
　また、バイポーラトランジスタ３３３のコレクタは、バイポーラトランジスタ３３３自身のベースと、バイポーラトランジスタ３４１のベースとに接続される。バイポーラトランジスタ３３１のコレクタは、バイポーラトランジスタ３３１自身のベースと、バイポーラトランジスタ３４１および３４２の接続点とに接続される。バイポーラトランジスタ３３１および３３３のエミッタは電源に接続される。 The collector of the bipolar transistor 333 is connected to the base of the bipolar transistor 333 itself and the base of the bipolar transistor 341. The collector of the bipolar transistor 331 is connected to the base of the bipolar transistor 331 itself and the connection point of the bipolar transistors 341 and 342. The emitters of bipolar transistors 331 and 333 are connected to a power source.
　バイポーラトランジスタ３４１および３４２はカスコード接続されており、また、バイポーラトランジスタ３４３および３４４もカスコード接続されている。バイポーラトランジスタ３４１のエミッタは電源に接続され、バイポーラトランジスタ３４４のエミッタは接地される。バイポーラトランジスタ３４２のコレクタは、バイポーラトランジスタ３４３のコレクタと接続される。また、バイポーラトランジスタ３４２のベースにはバイアス電圧Ｖｂ１が印加され、バイポーラトランジスタ３４３のベースにはバイアス電圧Ｖｂ２が印加される。これらのバイアス電圧を供給する回路（不図示）は、チャージポンプ３００内に配置される。コンデンサ３５０の一端は、バイポーラトランジスタ３４２および３４３の接続点と、チャージポンプ３００の出力端子とに接続され、他端は接地される。 The bipolar transistors 341 and 342 are cascode-connected, and the bipolar transistors 343 and 344 are also cascode-connected. The emitter of the bipolar transistor 341 is connected to the power supply, and the emitter of the bipolar transistor 344 is grounded. The collector of bipolar transistor 342 is connected to the collector of bipolar transistor 343. A bias voltage Vb1 is applied to the base of the bipolar transistor 342, and a bias voltage Vb2 is applied to the base of the bipolar transistor 343. A circuit (not shown) for supplying these bias voltages is arranged in the charge pump 300. One end of the capacitor 350 is connected to the connection point of the bipolar transistors 342 and 343 and the output terminal of the charge pump 300, and the other end is grounded.
　上述の構成において、定電流源３２１と、バイポーラトランジスタ３２２乃至３２５と、バイポーラトランジスタ３４３および３４４とからなる回路は、図１の電流スイッチング回路２４０と同様の機能を有する。また、定電流源３３５と、バイポーラトランジスタ３３１乃至３３４と、バイポーラトランジスタ３４１および３４２とからなる回路も、図１の電流スイッチング回路２４０と同様の機能を有する。これらの電流スイッチング回路のそれぞれは、出力信号ＶｏａおよびＶｏｂの値に応じてオンオフする。なお、バイポーラトランジスタ３４１乃至３４４は、特許請求の範囲に記載の第１乃至第４のトランジスタの一例である。 In the above-described configuration, a circuit including the constant current source 321, the bipolar transistors 322 to 325, and the bipolar transistors 343 and 344 has the same function as the current switching circuit 240 of FIG. Also, the circuit composed of the constant current source 335, the bipolar transistors 331 to 334, and the bipolar transistors 341 and 342 has the same function as the current switching circuit 240 of FIG. Each of these current switching circuits is turned on and off according to the values of the output signals Voa and Vob. Note that the bipolar transistors 341 to 344 are examples of first to fourth transistors recited in the claims.
　バイポーラトランジスタ３４１および３４２を流れる電流をＩｄ１とし、バイポーラトランジスタ３４３および３４４を流れる電流をＩｄ２とすると、次の式により表される制御電流Ｉｃｏｎがコンデンサ２２２に出力される。
　　Ｉｃｏｎ＝Ｉｄ１－Ｉｄ２ Assuming that the current flowing through bipolar transistors 341 and 342 is Id1, and the current flowing through bipolar transistors 343 and 344 is Id2, a control current Icon represented by the following equation is output to capacitor 222.
Icon = Id1-Id2
　この制御電流Ｉｃｏｎによりコンデンサ２２２は充放電され、その充放電電圧が制御電圧Ｖｃとして出力される。 The capacitor 222 is charged / discharged by the control current Icon, and the charge / discharge voltage is output as the control voltage Vc.
　図１４は、第３の実施の形態におけるチャージポンプ３００の動作の一例を示すタイミングチャートである。タイミングＴ１０において出力信号Ｖｏａがローレベルからハイレベルに移行し、その後のタイミングＴ１１において出力信号Ｖｏｂがローレベルからハイレベルに移行したものとする。また、その後のタイミングＴ１２において出力信号ＶｏａおよびＶｏｂはローレベルに移行したものとする。 FIG. 14 is a timing chart showing an example of the operation of the charge pump 300 according to the third embodiment. Assume that the output signal Voa shifts from the low level to the high level at the timing T10, and the output signal Vob shifts from the low level to the high level at the subsequent timing T11. Further, it is assumed that the output signals Voa and Vob are shifted to the low level at the subsequent timing T12.
　この場合に、タイミングＴ１０からタイミングＴ１２までの間にバイポーラスイッチ３４１および３４２がオン状態に移行して電流Ｉｄ１が増大する。一方、タイミングＴ１１からタイミングＴ１２までの間にバイポーラスイッチ３４３および３４４がオン状態に移行して電流Ｉｄ２が増大する。 In this case, the bipolar switches 341 and 342 are turned on between the timing T10 and the timing T12, and the current Id1 increases. On the other hand, the bipolar switches 343 and 344 are turned on between the timing T11 and the timing T12, and the current Id2 increases.
　ここで、バイポーラトランジスタ３４１および３４２はカスコード接続されているため、それらがオフ状態の期間においてリーク電流が低減し、電流Ｉｄ１はほぼ零となる。同様に、バイポーラトランジスタ３４３および３４４もカスコード接続されているため、それらがオフ状態の期間においてリーク電流が低減し、電流Ｉｄ２はほぼ零となる。これに対して、カスコード接続されていない比較例では、リーク電流が発生してしまう。図１４における点線は、比較例の電流および電圧である。 Here, since the bipolar transistors 341 and 342 are cascode-connected, the leakage current is reduced during the off-state period, and the current Id1 becomes almost zero. Similarly, since the bipolar transistors 343 and 344 are also cascode-connected, the leakage current is reduced during the off-state period, and the current Id2 becomes almost zero. On the other hand, in the comparative example in which the cascode connection is not performed, a leakage current occurs. The dotted lines in FIG. 14 are the current and voltage of the comparative example.
　また、電流Ｉｄ１およびＩｄ２の差分の制御電流Ｉｃｏｎは、タイミングＴ１０からタイミングＴ１１までの間に増大する。比較例では、リーク電流の発生により、この制御電流Ｉｃｏｎの増大量が小さくなってしまう。 In addition, the control current Icon which is the difference between the currents Id1 and Id2 increases from the timing T10 to the timing T11. In the comparative example, the increase amount of the control current Icon is reduced due to the generation of the leakage current.
　タイミングＴ１０からタイミングＴ１１までの間に流れる制御電流Ｉｃｏｎにより、コンデンサ３５０が充電され、制御電圧Ｖｃが上昇する。比較例では、リーク電流の発生により、この制御電圧Ｖｃの上昇量が小さくなってしまう。 The capacitor 350 is charged by the control current Icon that flows between the timing T10 and the timing T11, and the control voltage Vc increases. In the comparative example, the amount of increase in the control voltage Vc is reduced due to the occurrence of leakage current.
　このように、本技術の第３の実施の形態によれば、チャージポンプ３００内にカスコード接続したトランジスタを設けたため、チャージポンプ３００のリーク電流を低減することができる。 Thus, according to the third embodiment of the present technology, since the cascode-connected transistor is provided in the charge pump 300, the leakage current of the charge pump 300 can be reduced.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.
　なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
　なお、本技術は以下のような構成もとることができる。
（１）第１のバイポーラトランジスタと、
　前記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
　入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記接続点とに出力する比較部と
を具備するスイッチング回路。
（２）前記比較部の入力段は、一対の差動トランジスタを備える
前記（１）記載のスイッチング回路。
（３）前記一対の差動トランジスタは、バイポーラトランジスタである
前記（２）記載のスイッチング回路。
（４）前記一対の差動トランジスタは、ＭＯＳ(Metal Oxide Semiconductor)トランジスタである
前記（２）記載のスイッチング回路。
（５）第１のバイポーラトランジスタと、
　前記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
　入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記接続点とに出力する比較部と、
　一定の電流を供給するリカバー電流源と、
　前記リカバー電流源と前記第２のバイポーラトランジスタとに接続されたコンデンサと、
　前記コンデンサの充放電電圧に応じてゲインを変化させる可変ゲインアンプと
を具備する自動利得制御回路。
（６）前記比較部の入力は、前記可変ゲインアンプの入力である
前記（５）記載の自動利得制御回路。
（７）前記比較部の入力は、前記可変ゲインアンプの出力である
前記（５）記載の自動利得制御回路。
（８）入力信号と帰還信号との位相差および周波数差を検出して当該検出結果を示す第１および第２の出力信号を出力する検出器と、
　第１のバイポーラトランジスタと、
　前記第１のバイポーラトランジスタに第１の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
　前記第１の出力信号と当該第１の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記第１の接続点とに出力する第１の比較部と、
　第３のバイポーラトランジスタと、
　前記第３のバイポーラトランジスタに第２の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第４のバイポーラトランジスタと、
　前記第２の出力信号と当該第２の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を前記第３のバイポーラトランジスタのベースと前記第２の接続点とに出力する第２の比較部と、
　前記第２および第４のバイポーラトランジスタの接続点に接続されたコンデンサと、
　前記コンデンサの充放電圧に応じた周波数の周期信号を出力する電圧制御発振器と、
　前記周期信号を分周して前記帰還信号として前記検出器に帰還させる分周器と
を具備する位相同期回路。 In addition, this technique can also take the following structures.
(1) a first bipolar transistor;
A second bipolar transistor that is cascode-connected to the first bipolar transistor at a connection point and that has a constant bias voltage not applied below a threshold voltage applied to a base;
A switching circuit comprising a comparison unit that compares an input signal with a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point.
(2) The switching circuit according to (1), wherein the input stage of the comparison unit includes a pair of differential transistors.
(3) The switching circuit according to (2), wherein the pair of differential transistors is a bipolar transistor.
(4) The switching circuit according to (2), wherein the pair of differential transistors are MOS (Metal Oxide Semiconductor) transistors.
(5) a first bipolar transistor;
A second bipolar transistor that is cascode-connected to the first bipolar transistor at a connection point and that has a constant bias voltage not applied below a threshold voltage applied to a base;
A comparison unit that compares the input signal with a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point;
A recover current source for supplying a constant current;
A capacitor connected to the recovering current source and the second bipolar transistor;
An automatic gain control circuit comprising: a variable gain amplifier that changes a gain according to a charge / discharge voltage of the capacitor.
(6) The automatic gain control circuit according to (5), wherein an input of the comparison unit is an input of the variable gain amplifier.
(7) The automatic gain control circuit according to (5), wherein an input of the comparison unit is an output of the variable gain amplifier.
(8) a detector that detects a phase difference and a frequency difference between the input signal and the feedback signal and outputs first and second output signals indicating the detection result;
A first bipolar transistor;
A second bipolar transistor that is cascode-connected to the first bipolar transistor at a first connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
A pair of differential output signals indicating the comparison result by comparing the first output signal and a signal obtained by inverting the first output signal are obtained from the base of the first bipolar transistor and the first connection point. A first comparison unit that outputs to
A third bipolar transistor;
A fourth bipolar transistor that is cascode-connected to the third bipolar transistor at a second connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
A pair of differential output signals indicating the comparison result by comparing the second output signal with a signal obtained by inverting the second output signal and the base of the third bipolar transistor and the second connection point A second comparison unit for outputting to
A capacitor connected to a connection point of the second and fourth bipolar transistors;
A voltage-controlled oscillator that outputs a periodic signal having a frequency corresponding to the charge / discharge voltage of the capacitor;
A phase synchronization circuit comprising: a frequency divider that divides the periodic signal and feeds it back to the detector as the feedback signal.
　１００、１０１　電子装置
　１１０　アナログ信号出力部
　１２０　信号処理部
　１３０　位相同期回路
　１３１　位相／周波数検出器
　１３２　電圧制御発振器
　１３３　分周器
　１４０　信号処理部
　２００　ＡＧＣ回路
　２１０　可変ゲインアンプ
　２２０　ピーク検波回路
　２２１　参照電圧供給源
　２２２、３５０　コンデンサ
　２３０　バイアス電圧供給部
　２３１、２３３、２４１、２４２、２５１、２５２、２６１、２６２、２７１、２８１、３２２～３２５、３３１～３３４、３４１～３４４　バイポーラトランジスタ
　２３２　抵抗
　２４０　電流スイッチング回路
　２５０　比較部
　２６０、３２１、３３５　定電流源
　２７０、２８０　スイッチ
　２９０　リカバー電流源
　２９１　ＭＯＳトランジスタ
　３００　チャージポンプ
　３１０、３１１　インバータ 100, 101 Electronic device 110 Analog signal output unit 120 Signal processing unit 130 Phase synchronization circuit 131 Phase / frequency detector 132 Voltage controlled oscillator 133 Divider 140 Signal processing unit 200 AGC circuit 210 Variable gain amplifier 220 Peak detection circuit 221 Reference voltage Supply source 222, 350 Capacitor 230 Bias voltage supply unit 231, 233, 241, 242, 251, 252, 261, 262, 271, 281, 322 to 325, 331 to 334, 341 to 344 Bipolar transistor 232 Resistance 240 Current switching circuit 250 Comparison Unit 260, 321, 335 Constant Current Source 270, 280 Switch 290 Recover Current Source 291 MOS Transistor 300 Charge Pump 310, 311 Inverter

Claims (8)

  1. 　第１のバイポーラトランジスタと、
    　前記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
    　入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記接続点とに出力する比較部と
    を具備するスイッチング回路。     A first bipolar transistor;
    A second bipolar transistor that is cascode-connected to the first bipolar transistor at a connection point and that has a constant bias voltage not applied below a threshold voltage applied to a base;
    A switching circuit comprising a comparison unit that compares an input signal with a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point.
  2. 　前記比較部の入力段は、一対の差動トランジスタを備える
    請求項１記載のスイッチング回路。     The switching circuit according to claim 1, wherein an input stage of the comparison unit includes a pair of differential transistors.
  3. 　前記一対の差動トランジスタは、バイポーラトランジスタである
    請求項２記載のスイッチング回路。     The switching circuit according to claim 2, wherein the pair of differential transistors are bipolar transistors.
  4. 　前記一対の差動トランジスタは、ＭＯＳ(Metal Oxide Semiconductor)トランジスタである
    請求項２記載のスイッチング回路。     3. The switching circuit according to claim 2, wherein the pair of differential transistors are MOS (Metal Oxide Semiconductor) transistors.
  5. 　第１のバイポーラトランジスタと、
    　前記第１のバイポーラトランジスタに接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
    　入力信号と所定の参照信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記接続点とに出力する比較部と、
    　一定の電流を供給するリカバー電流源と、
    　前記リカバー電流源と前記第２のバイポーラトランジスタとに接続されたコンデンサと、
    　前記コンデンサの充放電電圧に応じてゲインを変化させる可変ゲインアンプと
    を具備する自動利得制御回路。     A first bipolar transistor;
    A second bipolar transistor that is cascode-connected to the first bipolar transistor at a connection point and that has a constant bias voltage not applied below a threshold voltage applied to a base;
    A comparison unit that compares the input signal with a predetermined reference signal and outputs a pair of differential output signals indicating the comparison result to the base of the first bipolar transistor and the connection point;
    A recover current source for supplying a constant current;
    A capacitor connected to the recovering current source and the second bipolar transistor;
    An automatic gain control circuit comprising: a variable gain amplifier that changes a gain according to a charge / discharge voltage of the capacitor.
  6. 　前記比較部の入力は、前記可変ゲインアンプの入力である
    請求項５記載の自動利得制御回路。     The automatic gain control circuit according to claim 5, wherein an input of the comparison unit is an input of the variable gain amplifier.
  7. 　前記比較部の入力は、前記可変ゲインアンプの出力である
    請求項５記載の自動利得制御回路。     The automatic gain control circuit according to claim 5, wherein an input of the comparison unit is an output of the variable gain amplifier.
  8. 　入力信号と帰還信号との位相差および周波数差を検出して当該検出結果を示す第１および第２の出力信号を出力する検出器と、
    　第１のバイポーラトランジスタと、
    　前記第１のバイポーラトランジスタに第１の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第２のバイポーラトランジスタと、
    　前記第１の出力信号と当該第１の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を前記第１のバイポーラトランジスタのベースと前記第１の接続点とに出力する第１の比較部と、
    　第３のバイポーラトランジスタと、
    　前記第３のバイポーラトランジスタに第２の接続点でカスコード接続され、閾値電圧を下回らない一定のバイアス電圧がベースに印加された第４のバイポーラトランジスタと、
    　前記第２の出力信号と当該第２の出力信号を反転した信号とを比較して当該比較結果を示す一対の差動出力信号を前記第３のバイポーラトランジスタのベースと前記第２の接続点とに出力する第２の比較部と、
    　前記第２および第４のバイポーラトランジスタの接続点に接続されたコンデンサと、
    　前記コンデンサの充放電圧に応じた周波数の周期信号を出力する電圧制御発振器と、
    　前記周期信号を分周して前記帰還信号として前記検出器に帰還させる分周器と
    を具備する位相同期回路。     A detector for detecting a phase difference and a frequency difference between the input signal and the feedback signal and outputting first and second output signals indicating the detection result;
    A first bipolar transistor;
    A second bipolar transistor that is cascode-connected to the first bipolar transistor at a first connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
    A pair of differential output signals indicating the comparison result by comparing the first output signal and a signal obtained by inverting the first output signal are obtained from the base of the first bipolar transistor and the first connection point. A first comparison unit that outputs to
    A third bipolar transistor;
    A fourth bipolar transistor that is cascode-connected to the third bipolar transistor at a second connection point and to which a constant bias voltage not lower than a threshold voltage is applied to a base;
    A pair of differential output signals indicating the comparison result by comparing the second output signal with a signal obtained by inverting the second output signal and the base of the third bipolar transistor and the second connection point A second comparison unit for outputting to
    A capacitor connected to a connection point of the second and fourth bipolar transistors;
    A voltage-controlled oscillator that outputs a periodic signal having a frequency corresponding to the charge / discharge voltage of the capacitor;
    A phase synchronization circuit comprising: a frequency divider that divides the periodic signal and feeds it back to the detector as the feedback signal.
PCT/JP2017/016371 2016-07-11 2017-04-25 Switching circuit, automatic gain control circuit and phase synchronization circuit WO2018012083A1 (en)

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Citations (7)

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JPS62158933U (en) * 1986-03-31 1987-10-08
JPH07262642A (en) * 1994-03-17 1995-10-13 Fujitsu Ltd Optical disk device
JPH08279734A (en) * 1995-04-05 1996-10-22 Canon Inc Charge pump circuit
JP2000151396A (en) * 1998-11-06 2000-05-30 Motorola Inc Phase comparator accompanied by frequency steering
JP2001285104A (en) * 2000-03-29 2001-10-12 Clarion Co Ltd Broadcast receiver
JP2002246905A (en) * 2001-01-06 2002-08-30 Samsung Electronics Co Ltd Charging-pump circuit and phase locked loop equipped there with
JP2013048554A (en) * 2006-11-30 2013-03-07 Mosaid Technologies Inc Circuit for clamping current in charge pump

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158933U (en) * 1986-03-31 1987-10-08
JPH07262642A (en) * 1994-03-17 1995-10-13 Fujitsu Ltd Optical disk device
JPH08279734A (en) * 1995-04-05 1996-10-22 Canon Inc Charge pump circuit
JP2000151396A (en) * 1998-11-06 2000-05-30 Motorola Inc Phase comparator accompanied by frequency steering
JP2001285104A (en) * 2000-03-29 2001-10-12 Clarion Co Ltd Broadcast receiver
JP2002246905A (en) * 2001-01-06 2002-08-30 Samsung Electronics Co Ltd Charging-pump circuit and phase locked loop equipped there with
JP2013048554A (en) * 2006-11-30 2013-03-07 Mosaid Technologies Inc Circuit for clamping current in charge pump

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