JP2011130518A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit capable of reducing current error irrespective of the state of a loop filter in a latter stage, and performing high-speed operation. <P>SOLUTION: The charge pump circuit includes a constant current source I1 connected between a terminal of VDD and a node N1, a constant current source I2 connected between a terminal of VSS and a node N2, a transistor MP1 connected between an input output terminal ICP and the node N1 and receiving an inputted signal UP, a transistor MN1 connected between the input output terminal ICP and the node N2 and receiving an inputted signal DN, a voltage amplifier 11 having an input side to be connected to the input output terminal ICP, a transistor MP2 connected between the node N1 and the output side of the voltage amplifier 11 and receiving an inverted signal UPB of the signal UP, and a transistor MN2 connected to the node N2 and the output side of the voltage amplifier 11 and receiving an inverted signal DNB of the signal DN. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a charge pump circuit that constitutes a phase locked loop (PLL).

  The phase-locked loop circuit is a circuit technology used in most electronic devices as a circuit that generates a signal having an arbitrary frequency from a reference frequency. A general PLL circuit includes a reference clock, a phase frequency comparator, a charge pump circuit, a loop filter, a voltage controlled oscillator (VCO), and a frequency divider. In the phase frequency comparator, the phases of the reference clock and the divider output (VCO output frequency divided by the divider) are compared, and the charge pump circuit is turned on / off according to the obtained phase difference. Then, charge / discharge of the capacity constituting the loop filter is performed. The output terminal of the loop filter is connected to the frequency control terminal of the VCO, and the oscillation frequency of the VCO is controlled according to the output voltage of the loop filter.

The PLL circuit performs a negative feedback operation such that the phase difference between the reference clock and the divider output is zero (that is, the frequency difference is also zero) by this one-round loop. At this time, when the frequency of the reference clock is f _REF , the oscillation frequency of the _VCO is f _VCO , and the frequency division ratio of the frequency divider is N, the relationship is f _VCO = f _REF × N.

  In addition to the “frequency synthesizer function” that generates a signal of an arbitrary frequency from the reference clock as described above, the PLL circuit inputs a deteriorated clock signal instead of the reference clock with a division ratio N of 1. It is also used as a “clock recovery function” for regenerating a clock signal with the VCO output.

  Examples of PLL circuit applications include wireless communications and audio / video equipment. Due to the demands for spectrum masks and high sound quality / high resolution, the PLL circuit has low phase noise, jitter, unnecessary spurious, and purity. A high output signal is required.

  The purity of the output signal of the PLL circuit can be calculated by theoretical analysis represented by Non-Patent Document 1 taking phase noise as an example, but each component of the PLL circuit actually has non-ideal operation. Therefore, it often deteriorates from the theoretical value.

  In view of this point, Patent Document 1 discloses a charge pump circuit that reduces “occurrence of overshoot current”, which is one of the non-ideal operations of the charge pump circuit, but depends on the state of the loop filter in the subsequent stage. Thus, the problem that the charge pump current error occurs is not solved. A conventional charge pump circuit 10E will be described below with reference to FIG.

  9 is connected to a conventional charge pump circuit 10E composed of constant current sources I1 and I2, p-type MOS transistors MP1 and MP2, n-type MOS transistors MN1 and MN2, and a current input / output terminal ICP of the charge pump circuit 10E. This is a circuit comprising the loop filter 20. The potential VDD and the potential VSS are the highest potential and the lowest potential of the circuit, respectively. The control voltage VC generated by the loop filter 20 is connected to a VCO (not shown) whose oscillation frequency increases when the control voltage VC increases.

  The signal UP is normally at the potential VDD, but when the phase difference between the reference clock and the divider output is compared by the phase frequency comparator, the phase of the divider output is delayed with respect to the reference clock. In addition, the potential VSS is set only during the period in which the phase difference occurs, and the p-type MOS transistor MP1 is turned on. At this time, the conventional charge pump circuit 10E discharges the set current of the constant current source I1 from the current input / output terminal ICP and charges the capacitor of the loop filter 20 with electric charge. As a result, the control voltage VC increases and the oscillation frequency of the VCO increases.

  Here, consider a state in which the signal UP is the potential VDD, that is, the p-type MOS transistor MP1 is OFF. In the absence of the p-type MOS transistor MP2, the current path from the constant current source I1 is cut off and the node N1 becomes floating, but the constant current source I1 becomes the potential VDD in the stray capacitance of the node N1 not explicitly shown in FIG. Charge up to. From this state, when the signal UP becomes the potential VSS and the p-type MOS transistor MP1 is turned on, the current of the input / output terminal ICP of the charge pump circuit 10E includes the node N1 and the control voltage VC in addition to the current from the constant current source I1. The current generated by the potential difference is also superimposed, and excess current, that is, overshoot current is discharged to the loop filter 20 until the potential difference becomes zero.

  The p-type MOS transistor MP2 has a drain terminal connected to the potential VSS and is ON / OFF controlled by a signal UPB obtained by inverting the signal UP. Therefore, when the p-type MOS transistor MP1 is ON, the p-type MOS transistor MP2 is OFF. When the p-type MOS transistor MP1 is OFF, the p-type MOS transistor MP2 is ON, so that the node N1 is floating. There is nothing. Therefore, the increase in the control potential VC due to the stray capacitance of the node N1 is reduced, and the overshoot current is reduced.

  Similarly, the signal DN is normally at the potential VSS. However, as a result of comparing the phase difference between the reference clock and the divider output by the phase frequency comparator, the phase of the divider output is advanced with respect to the reference clock. In this case, the potential becomes VDD only during the period in which the phase difference occurs, and the n-type MOS transistor MN1 is turned on. At this time, the conventional charge pump circuit 10E draws the set current of the constant current source I2 from the current input / output terminal ICP, and discharges the charge from the capacitance of the loop filter 20. As a result, the control voltage VC decreases and the oscillation frequency of the VCO decreases.

  Here, consider a state where the signal DN is the potential VSS, that is, the n-type MOS transistor MN1 is OFF. In the absence of the n-type MOS transistor MN2, the current path to the constant current source I2 is cut off and the node N2 is in a floating state. The constant current source I2 uses the potential VSS, which is not clearly shown in FIG. Discharge until From this state, when the signal DN becomes the potential VDD and the n-type MOS transistor MN1 is turned on, the current of the input / output terminal ICP of the charge pump circuit 10E includes the current from the constant current source I2, the node N2 and the control voltage VC. Current generated by the potential difference is also superimposed, and excess current, that is, overshoot current is drawn from the loop filter 20 until the potential difference becomes zero.

  The n-type MOS transistor MN2 has a drain terminal connected to the potential VDD and is ON / OFF controlled by a signal DNB obtained by inverting the signal DN. Therefore, when the n-type MOS transistor MN1 is ON, the n-type MOS transistor MN2 is OFF. When the n-type MOS transistor MN1 is OFF, the n-type MOS transistor MN2 is ON. Never become. Therefore, the potential drop of the control voltage VC due to the stray capacitance of the node N2 is reduced, and the overshoot current is reduced.

  Note that the p-type MOS transistor MP2 and the n-type MOS transistor MN2 have the same performance with respect to the potential VDD and the potential VSS supplied to the gate terminals, respectively, They have the same structure and are arranged adjacent to each other on the semiconductor integrated circuit.

JP 2002-330067 A

D.B.Leeson, “A simple model of feedback oscillator noise spectrum”, Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966.

  By the way, in general, the PLL circuit can achieve high performance such as performance improvement by a loop and high-speed response by speeding up the comparison operation in the phase frequency comparator. In the charge pump circuit 10E of FIG. 9, high speed operation of the p-type MOS transistors MP1 and MP2 and the n-type MOS transistors MN1 and MN2 is required.

  The switch function of the MOS transistor realizes ON / OFF by appropriately setting operating points of the drain terminal, the gate terminal, and the source terminal and changing the drain current ID that can be supplied. Normally, when ON, the MOS transistor is operated in a saturation region, and a drain current ID corresponding to the gate-source voltage VGS is supplied. In the saturation region, if the gate-source voltage VGS is constant, the drain current ID is constant even if the drain-source voltage VDS changes. However, in order to obtain a high-speed operation of the MOS transistor, the gate channel length Is shortened, the drain current ID is affected by channel length modulation depending on the drain-source voltage VDS even if the gate-source voltage VGS is constant.

  Here, in the conventional charge pump circuit 10E of FIG. 9, consider a case where the gate channel lengths of the p-type MOS transistors MP1 and MP2 are shortened in order to obtain high-speed operation. At this time, the drain-source voltage VDS of the P-type MOS transistor MP1 is the potential difference between the potential of the node N1 and the control voltage VC, and the drain-source voltage VDS of the p-type MOS transistor MP2 is the potential difference between the potential of the node N1 and the potential VSS. It becomes. Therefore, when one of the MOS transistors MP1 and MP2 is turned ON, the potential of the node N1, that is, the source potential of the MOS transistors MP1 and MP2, flows the drain current ID from the constant current source I1 due to the influence of channel length modulation. The drain-source voltage VDS and the gate-source voltage VGS, which are necessary for the above, are appropriately changed. This potential fluctuation occurs when the MOS transistors MP1 and MP2 are turned on / off, and charges are charged and discharged in the stray capacitance of the node N1, so that an error occurs in the set current by the constant current source I1.

  Similarly, in the conventional charge pump circuit 10E of FIG. 9, a case is considered in which the gate channel lengths of the n-type MOS transistors MN1 and MN2 are shortened in order to obtain high-speed operation. At this time, the drain-source voltage VDS of the n-type MOS transistor MN1 is the potential difference between the potential of the node N2 and the control voltage VC, and the drain-source voltage VDS of the n-type MOS transistor MN2 is the potential difference between the potential of the node N2 and the potential VDD. It becomes. Therefore, when one of the MOS transistors MN1 and MN2 is turned on, the potential of the node N2, that is, the source potential of the MOS transistors MN1 and MN2, flows the drain current ID from the constant current source I2 due to the influence of channel length modulation. The drain-source voltage VDS and the gate-source voltage VGS, which are necessary for the above, are appropriately changed. This potential fluctuation occurs when the MOS transistors MN1 and MN2 are switched on and off, and charges are charged and discharged in the stray capacitance of the node N2. Therefore, an error occurs in the set current by the constant current source I2.

  Further, the magnitude of the potential fluctuation at the nodes N1 and N2 differs depending on the state of the loop filter 20, that is, the state of the control voltage VC, and the error given to the constant current sources I1 and I2 differs. There is also a problem that the discharge current and the sink current become unbalanced and the purity of the output signal of the PLL circuit is deteriorated.

  An object of the present invention is to provide a charge pump circuit that solves the above-described problems, reduces a current error regardless of the state of a subsequent loop filter, and is capable of high-speed operation.

To achieve the above object, a charge pump circuit according to a first aspect of the present invention includes a first constant current source connected between a first power supply terminal and a first node, and a second power supply terminal. And a second constant current source connected between the first node and the second node, and a first conductivity type first connected between the input / output terminal and the first node and receiving a first signal. A second conductive type second transistor connected between the input / output terminal and the second node and receiving a second signal, and a voltage at which an input side is connected to the input / output terminal An amplifier; a first transistor of the first conductivity type connected to the output side of the first node and the voltage amplifier and receiving an inverted signal of the first signal; the second node; and the voltage amplifier A second conductivity type connected to the output side of the first input and receiving an inverted signal of the second signal A fourth transistor, characterized in that it comprises.
According to a second aspect of the present invention, in the charge pump circuit according to the first aspect, the voltage amplifier is replaced with a voltage follower circuit.
According to a third aspect of the present invention, in the charge pump circuit according to the first or second aspect, the first transistor is a first transmission gate, the second transistor is a second transmission gate, and the third transistor is the third transmission gate. The third transistor is replaced with a third transmission gate, the fourth transistor is replaced with a fourth transmission gate, and the first transmission gate is controlled to be turned ON / OFF by the first signal and its inverted signal. The second transmission gate controls ON / OFF by the second signal and its inverted signal, and the third transmission gate controls the first signal by its first signal and its inverted signal. Control ON / OFF opposite to ON / OFF of transmission gate, Serial fourth transmission gate, said second signal and by its inverted signal, and to control the ON / OFF in ON / OFF and the reverse of the second transmission gate, characterized in that.

  According to the charge pump circuit of the present invention, the input side of the voltage amplifier or the voltage follower circuit is connected to the input / output terminal, and the output side is connected to the common connection point of the third and fourth transistors. The connection point is controlled to be the same potential as the input / output terminal. Therefore, the voltage across the first and third transistors and the voltage across the second and fourth transistors are the same. Therefore, the current error of the charge pump circuit can be reduced and a high-speed operation can be performed regardless of the state of the loop filter at the subsequent stage, and a PLL output signal with higher purity can be obtained.

1 is a circuit diagram of a charge pump circuit 10A showing a first embodiment of the present invention. It is a circuit diagram of the charge pump circuit 10B which shows the 2nd Embodiment in this invention. It is a circuit diagram of the charge pump circuit 10C which shows the 3rd Embodiment in this invention. It is a circuit diagram of charge pump circuit 10D which shows the 4th Embodiment in this invention. 3 is a diagram illustrating an example of an operation confirmation circuit of the charge pump circuit block 10. FIG. FIG. 6 is a waveform diagram showing an example of an input signal to the charge pump circuit block 10 of the operation check circuit shown in FIG. 5. FIG. 6 is a waveform diagram showing an example of an output current when the signal of FIG. 6 is input when the charge pump circuit block 10 of the operation check circuit shown in FIG. 5 is a conventional charge pump circuit 10E. FIG. 6 is a waveform diagram showing an example of an output current when the signal of FIG. 6 is input when the charge pump circuit block 10 of the operation check circuit shown in FIG. 5 is the charge pump circuit 10A of the first embodiment of the present invention. . It is a circuit diagram which shows the example of the conventional charge pump circuit 10E and the loop filter 20. FIG.

  Hereinafter, some examples relating to embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are used for elements representing the same configuration, operation and effect.

First Embodiment FIG. 1 shows a charge pump circuit 10A showing a first embodiment of the present invention. The charge pump circuit 10A shown in FIG. 1 includes constant current sources I1 and I2, p-type MOS transistors MP1 and MP2, n-type MOS transistors MN1 and MN2, and a voltage amplifier 11. The potential VDD and the potential VSS are the highest potential and the lowest potential of the circuit, respectively.

  In the charge pump circuit 10A in FIG. 1, when the signal UP is at the potential VSS at the current input / output terminal ICP connected to the subsequent loop filter, the p-type MOS transistor MP1 is turned on and the input is connected to the terminal at the potential VDD. A constant current is discharged from the output of the constant current source I1 to the subsequent loop filter. When the signal DN is at the potential VDD, the n-type MOS transistor MN1 is turned on, and a constant current is drawn from the subsequent loop filter to the input of the constant current source I2 connected to the terminal of the potential VSS.

  Further, the source terminal of the p-type MOS transistor MP2 is connected to a node N1 that is a connection point between the output of the constant current source I1 and the source terminal of the p-type MOS transistor MP1, and is turned on / off by a signal UPB obtained by inverting the signal UP. Is done. Similarly, the source terminal of the n-type MOS transistor MN2 is connected to a node N2, which is a connection point between the input of the constant current source I2 and the source terminal of the n-type MOS transistor MN1, and is turned on / off by a signal DNB obtained by inverting the signal DN. OFF-controlled. The voltage amplifier 11 functions as a buffer (buffer) that detects the voltage of the subsequent router filter connected to the current input / output terminal ICP and supplies it to the drain terminals of the p-type MOS transistor MP2 and the n-type MOS transistor MN2. To do.

  Here, when the signal UP is the potential VDD and the signal UPB is the potential VSS, the p-type MOS transistor MP1 is turned off, but the p-type MOS transistor MP2 is turned on, so that the constant current source I1 to the voltage amplifier 11 is turned on. A current path is created.

  On the other hand, when the signal UP is the potential VSS and the signal UPB is the potential VDD, the p-type MOS transistor MP2 is turned off, but the p-type MOS transistor MP1 is turned on, so that the current from the constant current source I1 to the current output terminal ICP. A route is made.

  Further, since the voltage of the subsequent loop filter connected to the current input / output terminal ICP by the voltage amplifier 11, that is, the drain voltage of the p-type MOS transistor MP1, is supplied to the drain terminal of the p-type MOS transistor MP2. Regardless of the state of the loop filter, the drain-source voltage VDS of the p-type MOS transistor MP1 and the drain-source voltage VDS of the p-type MOS transistor MP2 are the same, and the potential of the node N1 is always a constant value.

  From the above, it is possible to avoid generation of an error current due to potential fluctuation of the node N1. As an additional effect, the drain-source voltage VDS of each MOS transistor MP1 and MP2 does not change before and after the ON / OFF control by the signal UP and the signal UPB, so that the switching operation is immediately stabilized and the high-speed operation is performed. Is possible.

  Similarly, when the signal DN is the potential VSS and the signal DNB is the potential VDD, the n-type MOS transistor MN1 is turned off, but the n-type MOS transistor MN2 is turned on, so that the voltage amplifier 11 supplies the constant current source I2. A current path is created.

  On the other hand, when the signal DN is the potential VDD and the signal UDB potential VSS, the n-type MOS transistor MN2 is turned off, but the n-type MOS transistor MN1 is turned on, so that the current from the current output terminal ICP to the constant current source I2 A route is made.

  Furthermore, since the voltage of the subsequent loop filter connected to the current input / output terminal ICP by the voltage amplifier 11, that is, the drain voltage of the n-type MOS transistor MN1 is supplied to the drain of the n-type MOS transistor MN2, Regardless of the state of the loop filter, the drain-source voltage VDS of the n-type MOS transistor MN1 and the drain-source voltage VDS of the n-type MOS transistor MN2 are the same, and the potential of the node N2 is always a constant value.

  From the above, the generation of error current due to the potential fluctuation of the node N2 can be reduced. As an additional effect, since the drain-source voltage VDS of the MOS transistors MN1 and MN2 does not change before and after the ON / OFF control by the signal DN and the signal DNB, the switching operation is immediately stabilized and the high-speed operation is performed. Is possible.

<Second Embodiment>
FIG. 2 shows a charge pump circuit 10B showing a second embodiment of the present invention. This charge pump circuit 10B is obtained by replacing the voltage amplifier 11 in the charge pump circuit 10A of the first embodiment of FIG. 1 with a voltage follower circuit 12 in which the output terminal of the operational amplifier is connected to the inverting input terminal. The voltage follower circuit 12 can operate in the same manner as the voltage amplifier 11, and the charge pump circuit 10B in FIG. 2 can also realize a reduction in error current and high-speed operation.

<Third Embodiment> FIG. 3 shows a charge pump circuit 10C according to a third embodiment of the present invention. The charge pump circuit 10C includes a transmission gate TM1 in which the p-type MOS transistor MP1 in the charge pump circuit 10A of the first embodiment of FIG. 1 is connected to the source terminal and drain terminal of a p-type MOS transistor and an n-type MOS transistor. The n-type MOS transistor MN1 is replaced with the same transmission gate TM2 as the transmission gate TM1, the p-type MOS transistor MP2 is replaced with the same transmission gate TM3 as the transmission gate TM1, and the n-type MOS transistor MN2 is the same as the transmission gate TM1. The transmission gate TM4 is replaced.

  Signal UP is input to the gate terminal of the p-type MOS transistor of transmission gate TM1, and signal UPB is input to the gate terminal of the n-type MOS transistor. Signal UPB is input to the gate terminal of the p-type MOS transistor of transmission gate TM3, and signal UP is input to the gate terminal of the n-type MOS transistor. Similarly, the signal DN is input to the gate terminal of the n-type MOS transistor of the transmission gate TM2, and the signal DNB is input to the gate terminal of the p-type MOS transistor. Signal DNB is input to the gate terminal of the n-type MOS transistor of transmission gate TM4, and signal DN is input to the gate terminal of the p-type MOS transistor.

  Each of the transmission gates TM1 to TM4 can operate in the same manner as each transistor in the charge pump circuit 10A of the first embodiment of FIG. 1, and the charge pump circuit of FIG. be able to.

<Fourth Embodiment>
FIG. 4 shows a charge pump circuit 10D showing a fourth embodiment of the present invention. This charge pump circuit 10D is obtained by replacing the voltage amplifier 11 in the charge pump circuit 10C of the third embodiment of FIG. 3 with a voltage follower circuit 12 in which the output terminal of the operational amplifier is connected to the inverting input terminal. The voltage follower circuit 12 can operate in the same manner as the voltage amplifier 11, and the charge pump circuit 10D of FIG. 4 can also realize a reduction in error current and high-speed operation.

<Examples of error current reduction and high-speed operation>
FIG. 5 shows an example of the operation confirmation circuit of the charge pump circuit. In FIG. 5, a charge pump circuit block 10 blocks the conventional charge pump circuit 10E of FIG. 9 or the charge pump circuits 10A to 10D of any of the first to fourth embodiments shown in FIGS. It has become.

  Here, the signals UP, UPB, DN, DNB, the current input / output terminal ICP, the potentials VDD, VSS are the same as those of the conventional charge pump circuit 10E of FIG. 9 or the first to fourth embodiments shown in FIGS. Are the same as those in the charge pump circuits 10A to 10D, and have the same function.

  In FIG. 5, the charge pump circuit block 10 is supplied with the DC voltage VDD [V] from the constant voltage source E1 at the terminal of the potential VDD, and the terminal of the potential VSS is grounded. The pulse voltage UP [V] generated by the pulse generator P1 and the pulse voltage UPB [V] obtained by inverting the pulse voltage UP [V] by the inverter INV1 are input to the terminals UP and UPB, respectively. Similarly, the pulse voltage DN [V] generated by the pulse generator P2 and the pulse voltage DNB [V] obtained by inverting the pulse voltage DN [V] by the inverter INV2 are input to the terminals DN and DNB, respectively.

  Incidentally, the current input / output terminal ICP of the charge pump circuit is generally connected to the loop filter 20 shown in FIG. 9, and performs a charge / discharge operation with respect to the capacitor constituting the loop filter 20. Therefore, in the state where the loop filter 20 is connected, the voltage of the current input / output terminal ICP always changes according to the charge / discharge operation, and thus is not suitable for checking the operation of the charge pump circuit itself.

  Therefore, in FIG. 5, a constant voltage source E2 is connected instead of the loop filter 20, and the DC voltage VC [V] is artificially supplied to the current input / output terminal ICP, and is input / output from the current input / output terminal ICP. Check the current with ammeter A1. The bias resistor R1 between the ammeter A1 and the constant voltage source E2 is for preventing the voltage of the current input / output terminal ICP from being fixed at VC [V], and affects the circuit operation. The resistance value should be as small as possible. The measured value of the ammeter A1 indicates a positive value when the current from the charge pump circuit block 10 flows in the direction of arrow a in FIG. 5, and indicates a negative value when it flows in the direction opposite to the arrow.

  6A to 6D show time waveform examples of UP [V], UPB [V], DN [V], and DNB [V] when VDD [V] is 1.8V. . Here, UP [V] and UPB [V], and DN [V] and DNB [V] are in an inverted relationship.

  FIG. 7 shows the output observed by the ammeter A1 when the signals (a) to (d) of FIG. 6 are inputted, with the charge pump circuit block 10 shown in FIG. 5 being the conventional charge pump circuit 10E shown in FIG. An example of a current waveform is shown. At this time, the constant current source I1 and the constant current source I2 of the conventional charge pump circuit 10E shown in FIG. 9 are set to 20 μA. 7A is when VC [V] = VDD [V] × 0.25, and FIG. 7B is when VC [V] = VDD [V] × 0.5, FIG. 7C shows an example of an output current waveform when VC [V] = VDD [V] × 0.75.

  In the example of FIG. 7, in each waveform, an overshoot current or an undershoot current is generated at the current change point, and time is required until the output current reaches the set currents of the constant current source I1 and the constant current source I2. I need it.

  8 is the charge pump circuit block 10A of the first embodiment shown in FIG. 1 in FIG. 5, and the ammeter when the signals (a) to (d) of FIG. 6 are input. An example of the output current waveform observed at A1 is shown. At this time, the constant current source I1 and the constant current source I2 of the charge pump circuit 10A according to the first embodiment shown in FIG. 1 are set to 20 μA. Similarly to FIG. 7, (a) in FIG. 8 is VC [V] = VDD [V] × 0.25, and (b) in FIG. 8 is VC [V] = VDD [V] × FIG. 8C shows an example of an output current waveform when VC [V] = VDD [V] × 0.75 when 0.5.

  In the example of FIG. 8, in each waveform, the overshoot current and undershoot current are reduced at the current change point, and the time until the output current reaches the set current of the constant current source I1 and the constant current source I2 is set. short. As a result, according to the charge pump circuit 10A of the first embodiment of the present invention, it was confirmed that the error current was reduced as compared with the conventional charge pump circuit 10E and high-speed operation could be realized. Also, the charge pump circuits 10B to 10D of the second to fourth embodiments of the present invention can operate in the same manner as the charge pump circuit 10A of the first embodiment, and thus the same effect can be obtained. .

The present invention is not limited to the first to fourth embodiments described above, and can be expanded to various examples that can be easily configured by those skilled in the art using the technology of the present invention. For example, the transistor is not limited to the MOS type, and a bipolar transistor can also be used. In this case, the gate terminal is replaced with the base terminal, the drain terminal is replaced with the collector terminal, and the source terminal is replaced with the emitter terminal.

10: Charge pump circuit block 10A to 10E: Charge pump circuit 11: Voltage amplifier 12: Voltage follower circuit 20: Loop filter ICP: Current input / output terminal N1, N2: Node VDD, VSS: Potential UP, UPB, DN, DNB: Input signal VC: Control voltage I1, I2: Constant current source MP1, MP2: p-type MOS transistor MN1, MN2: n-type MOS transistor TM1-TM4: Transmission gate P1, P2: Pulse generator INV1, INV2: Inverter A1: Current Total R1: Bias resistance E1, E2: Constant voltage source

Claims (3)

A first constant current source connected between the first power supply terminal and the first node;
A second constant current source connected between the second power supply terminal and the second node;
A first transistor of a first conductivity type connected between an input / output terminal and the first node and receiving a first signal;
A second transistor of a second conductivity type connected between the input / output terminal and the second node and receiving a second signal;
A voltage amplifier having an input side connected to the input / output terminal;
A third transistor of a first conductivity type connected to the first node and the output side of the voltage amplifier and receiving an inverted signal of the first signal;
A fourth transistor of the second conductivity type connected to the second node and the output side of the voltage amplifier and receiving an inverted signal of the second signal;
A charge pump circuit comprising: The charge pump circuit according to claim 1,
A charge pump circuit, wherein the voltage amplifier is replaced with a voltage follower circuit. The charge pump circuit according to claim 1 or 2,
The first transistor is a first transmission gate, the second transistor is a second transmission gate, the third transistor is a third transmission gate, and the fourth transistor is a fourth transmission gate. Respectively,
The first transmission gate controls ON / OFF by the first signal and its inverted signal,
The second transmission gate controls ON / OFF by the second signal and its inverted signal,
The third transmission gate controls ON / OFF opposite to the ON / OFF of the first transmission gate by the first signal and its inverted signal,
The fourth transmission gate is configured to control ON / OFF in reverse to the ON / OFF of the second transmission gate by the second signal and its inverted signal.
A charge pump circuit.

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