KR100293769B1 - Charge pumping circuit and PLL frequency synthesizer - Google Patents

Abstract

The charge pumping circuit of the present invention includes a constant current source, a switch element, a first MOS transistor, a second MOS transistor, and a switching-off circuit. The constant current source generates and outputs a current having a constant current value. The switch element turns on when the input signal is active and outputs the current determined by the constant current source. A current outputted from the switch element flows to the first MOS transistor. The second MOS transistor forms a current mirror circuit together with the first MOS transistor and outputs a current having a current value based on the current flowing through the first MOS transistor as one of a charge current and a discharge current. The switching-off circuit turns off the second MOS transistor by charging or discharging the gate of the second MOS transistor when the input signal is inactive.

Description

Charge pumping circuit and PLL frequency synthesizer

The present invention relates to a phase locked loop (PLL) frequency synthesizer including a charge pumping circuit and a charge pumping circuit, and more particularly to a PLL (phase locked loop) frequency synthesizer having a control for controlling the voltage controlled oscillator to oscillate at a target frequency To a charge pumping circuit for outputting a voltage.

3 shows a PLL frequency synthesizer including a charge pumping circuit.

The PLL frequency synthesizer includes a phase comparator 71, a charge pumping circuit 72, a loop filter 23, a voltage controlled oscillator (VCO) 73, and a frequency divider 74.

The phase comparator 71 detects the phase difference between the comparison signal fs and the reference signal fr. When the phase of the comparison signal is delayed relative to the phase of the reference signal, the phase comparator 71 outputs the phase error / up signal 101. If the phase of the comparison signal is ahead of the phase of the reference signal, the phase comparator 71 outputs the phase error / down signal 102.

The charge pumping circuit 72 charges the loop filter 23 by receiving the phase error / up signal 101 and discharges the loop filter 23 by receiving the phase error /

The loop filter 23 generates and outputs a control voltage Vc for oscillating the voltage controlled oscillator 73 at the target frequency in accordance with the charge and discharge current output from the charge pumping circuit 72. [

The voltage-controlled oscillator 73 outputs a signal having a frequency controlled by the control voltage Vc as the oscillation output signal fv. The frequency divider 74 divides the frequency of the oscillation output signal fv and outputs the comparison signal fs to the phase comparator 71.

This PLL frequency synthesizer operates so that the comparison signal fs is in phase with the reference signal fr, thereby controlling the voltage-controlled oscillator 73 to oscillate at the target frequency.

The configuration of the conventional charge pumping circuit 72 shown in FIG. 3 will be described with reference to FIG.

The charge pumping circuit shown in Fig. 4 includes a constant current source 20, a loop filter 23, p-channel MOS transistors 41 and 42, and n-channel MOS transistors 43 and 44.

The constant current source 20 is constituted by p-channel MOS transistors 13 and 14, an n-channel MOS transistor 15 and a resistor 16, and generates and outputs a constant current. The p-channel and n-channel MOS transistors 42 and 43 output the current generated by the constant current source 20.

The source of the p-channel MOS transistor 41 is connected to the power supply and its gate receives the phase error / up signal 101 and its drain is connected to the source of the p-channel MOS transistor 42. If a phase error / up signal 101 is active (low level), the p- channel MOS transistor 41 is turned on and the charging current to the current set by the p- channel MOS transistor 42 to the loop filter (23) I _up .

The source of the n-channel MOS transistor 44 is grounded, its gate receives the phase error / down signal 102, and its drain is connected to the source of the n-channel MOS transistor 43. When the phase error / down signal 102 becomes active (high level), the n-channel MOS transistor 44 is turned on and the current determined by the n-channel MOS transistor 43 is supplied from the loop filter 23 to the discharge current I _Down .

The loop filter 23 is charged and discharged by the charging current I _up and the discharging current I _Down to generate a control voltage and output this voltage to the VCO.

The operation of a conventional charge pumping circuit having such a configuration will be described.

In the charge pumping circuit shown in Fig. 4, when the phase error / up signal 101 is active, the p-channel MOS transistor 41 is turned on. As a result, the charge current I _up determined by the p-channel MOS transistor 42 is output to the loop filter 23, and the control voltage output from the loop filter 23 increases.

When the phase error / down signal 102 is active, the n-channel MOS transistor 44 is turned on. As a result, the discharge current I _Down determined by the n-channel MOS transistor 43 is discharged from the loop filter 23, and the control voltage output from the loop filter 23 decreases.

In this charge pumping circuit, the phase error / up or down signal 101 or 102 is applied to the p-channel or n-channel MOS transistor 42 or 44 through the gate diffusion capacitance of the p- or it causes the variation of the source potential V _GS 43).

For this reason, the charging current I _up and the discharging current I _Down determined by the MOS transistors 42 and 43 vary. 5A, noise is superimposed on the control voltage Vc output from the loop filter 23 at intervals of 1 / reference signal fr. When the spectrum of the oscillation output signal fv from the VCO controlled by the noise-superimposed control voltage Vc is measured, it is confirmed that the reference leakage due to the reference frequency component overlaps the signal fv as shown in FIG. 5B Respectively.

In this charge pumping circuit, the constant current output voltage V _DS between the drain and source of the p-channel and n-channel MOS transistors 42 and 43 depends on the state of the control voltage Vc. For this reason, the current gain changes and the settling time becomes unstable.

Another example of the charge pumping circuit for suppressing the fluctuation in the current gain will be described with reference to Fig. 4, the same reference numerals as those in FIG. 4 denote the same parts, and a description thereof will be omitted.

The charge pumping circuit shown in Figure 6 includes a first switching circuit 81, a first current source 82, a second switching circuit 83, a second current source 84, an output circuit 85 and inverters 65 and 66 ).

The first switching circuit 81 is composed of a p-channel MOS transistor 62 and npn transistors 51 and 55. The first current source 82 is comprised of an npn transistor 52 and a resistor 63. The second switching circuit 83 is composed of a p-channel MOS transistor 61 and npn transistors 54 and 56. The second current source 84 is comprised of an npn transistor 53 and a resistor 64. The output circuit 85 is composed of p-channel MOS transistors 57 and 60 and n-channel MOS transistors 58 and 59.

The inverter 65 inverts the logic level of the phase error / up signal 101 and outputs the inverted signal to the first switching circuit 81. [ The inverter 66 inverts the logic level of the phase error / down signal 102 and outputs the inverted signal to the second switching circuit 83.

In the first switching circuit 81, the source of the p-channel MOS transistor 62 is connected to the power source, its drain is connected to the collector of the npn transistor 51, and its gate is connected to the p- As shown in FIG. The collector of the npn transistor 55 is connected to the power supply and its base receives the phase error / up signal 101, and its emitter is connected to the emitter of the npn transistor 51. The base of the npn transistor 51 receives the output from the inverter 65.

In the first current source 82 the collector of npn transistor 52 is connected to the emitter of npn transistors 51 and 55 and its emitter is grounded through resistor 63 and its base receives the reference voltage Vref do.

In the second switching circuit 83, the source of the p-channel MOS transistor 61 is connected to the power source, its drain is connected to the collector of the npn transistor 54, and its gate is connected to the p- As shown in FIG. The collector of the npn transistor 56 is connected to the power supply and its base receives the output from the inverter 66 and its emitter is connected to the emitter of the npn transistor 54. The base of the npn transistor 54 receives the phase error / down signal 102.

In the second current source 84, the cooler of the npn transistor 53 is connected to the emitter of npn transistors 55 and 56, the emitter of which is grounded through a resistor 64, .

In the output circuit 85, the source of the p-channel MOS transistor 57 is connected to the power supply, and the drain thereof is connected to the loop filter 23. The p-channel MOS transistor 57 forms a current mirror circuit together with the p-channel MOS transistor 62. The p-channel MOS transistor 57 outputs to the loop filter 23 a current having a current value based on the current flowing through the source and the drain of the p-channel MOS transistor 62 as the charging current I _up .

The source of the p-channel MOS transistor 60 is connected to a power source, its source is connected to the power source, and its drain is connected to the drain of the n-channel MOS transistor 59. The p-channel MOS transistor 60 together with the p-channel MOS transistor 61 forms a current mirror circuit. a current having a current value based on the current flowing through the source and the drain of the p-channel MOS transistor 61 flows through the source and the drain of the p-channel MOS transistor 60.

The drain of the n-channel MOS transistor 59 is connected to the drain of the p-channel MOS transistor 60, the source of the n-channel MOS transistor 59 is grounded, As shown in FIG.

The gate of the n-channel MOS transistor 58 is grounded, its gate is connected to the gate of the n-channel MOS transistor 59, and the drain of the n-channel MOS transistor 58 is connected to the p- And to the drain and loop filter 23 of FIG. The n-channel MOS transistor 58 forms a current mirror circuit together with the n-channel MOS transistor 59. The n-channel MOS transistor 58 outputs to the loop filter 23 a current having a current value based on the current flowing through the source and drain of the n-channel MOS transistor 59 as the discharge current I _down .

The operation of the charge pumping circuit having such a configuration will be described.

When the phase error / up signal 101 becomes active (low level), the inverter 65 outputs a high level signal, and the differential amplifier consisting of the npn transistors 51 and 55 outputs the npn transistor 52 and the resistor And 63, respectively. This constant current also flows through the source and drain of the p-channel MOS transistor 62. As a result, a current having a current value based on a constant current flows through the source and drain of the p-channel MOS transistor 57 as a charge current I _up and is output to the loop filter 23.

When the phase error / down signal 102 becomes active (high level), inverter 66 outputs a low-level signal such that the differential amplifier consisting of npn transistors 54 and 56 is connected to npn transistor 53 and resistor And the current determined by the current source formed by the current source 64 flows. This constant current also flows through the source and drain of the p-channel MOS transistor 61. Therefore, a current having a current value based on a constant current flows through the source and the drain of the p-channel MOS transistor 60 and the source and the drain of the n-channel MOS transistor 59.

a current having a current value based on the current flowing through the source and drain of the n-channel MOS transistor 59 flows through the source and the drain of the n-channel MOS transistor 58 as the discharge current I _D , Is discharged.

In this charge pumping circuit, since the npn transistors 52 and 53 are not disposed on the output stage, the current gain is not dependent on the output stage. Therefore, the stabilization time is stabilized, and the control residual pressure Vc does not increase. Since the npn transistors 52 and 53, which respectively form the current sources 82 and 84, are not disposed on the output stage, fluctuations in the output current due to the switching operation do not occur.

In this charge pumping circuit, however, when the npn transistors 51 and 54 are turned off, the gate of the p-channel MOS transistor 57 is not quickly charged, or the gate of the n- It is not discharged quickly. Thus, since the p-channel and n-channel MOS transistors 57 and 58 require a long turn-off time, the linearity of the output currents (charge current I _up and discharge current I _down ) for the phase error signal deteriorates . As a result, the reference leakage and the jitter increase.

In this charge pumping circuit, because the npn transistors 51 and 54 as bipolar transistors receive the phase error signal, they are CMOS (Complementary Metal-Oxide Semiconductor) -ECL Circuit combinational logic) is required, resulting in a large-scale circuit.

The conventional charge pumping circuit has the following problems.

(1) Since the turn-off time of the output transistor is long, the linearity of the output current with respect to the phase error signal deteriorates, and the reference leakage and jitter become large.

(2) A CMOS-ECL level converter is required for connection with a general digital phase comparator.

It is therefore an object of the present invention to provide a charge pumping circuit and a PLL frequency synthesizer that can maintain the linearity of the output current with respect to the phase error signal.

It is another object of the present invention to provide a charge pumping circuit and a PLL frequency synthesizer which can reduce a reference leakage without requiring any specific circuit when connecting to a phase comparator.

In order to achieve the above objects, according to the present invention, there is provided a constant current source comprising: a constant current source for generating and outputting a current having a constant current value; switch means for turning on when an input signal is active and outputting a current determined by a constant current source; And a current mirror circuit is formed with the first MOS transistor to output a current having a current value based on a current flowing through the first MOS transistor as one of a charge current and a discharge current And a switching-off means for turning off the second MOS transistor by putting or discharging the gate of the second MOS transistor when the input signal is inactive, is provided.

1 is a circuit diagram showing a charge pumping circuit according to a first embodiment of the present invention;

2 is a circuit diagram showing a charge pumping circuit according to a second embodiment of the present invention;

3 is a diagram showing a configuration of a PLL frequency synthesizer.

4 is a circuit diagram showing a conventional charge pumping circuit.

Fig. 5A is a waveform chart for explaining noise superimposed on the control voltage shown in Fig. 4. Fig.

5B is a waveform chart for explaining the frequency spectrum of the oscillation output signal;

6 is a circuit diagram showing another conventional charge pumping circuit;

Description of the Related Art

1, 2, 6, 8: n-channel MOS transistor

3, 4, 5, 7: p-channel MOS transistor

17, 18: Inverter

73: Voltage controlled oscillator

101: phase error / up signal

102: Phase error / down signal

123: Loop filter

120: constant current source

121, 122: switching-off circuit

The present invention will be described in detail below with reference to the accompanying drawings.

(Embodiment 1)

Figure 1 illustrates a charge pumping circuit in accordance with the present invention.

The charge pumping circuit of the first embodiment includes a constant current source 120, n-channel MOS transistors 1, 2, 6 and 8, p-channel MOS transistors 3, 4, 5 and 7, (121 and 122), and inverters (17 and 18).

The inverter 17 inverts the logic level of the phase error / up signal 101 and outputs the inverted signal to the switching-off circuit 121. The inverter 18 inverts the logic level of the phase error / down signal 102 and outputs the inverted signal to the switching-off circuit 122.

The gate of the n-channel MOS transistor 1 receives the output from the inverter 17 and its drain is connected to the drain of the p-channel MOS transistor 5, Drain. When the phase error / up signal 101 is activated (low level), the n-channel MOS transistor 1 is turned on and the current determined by the n-channel MOS transistor 2 flows through the source and the drain. A series circuit composed of two MOS transistors 1 and 2 forms a constant current switching circuit.

The gate of the n-channel MOS transistor 2 is connected to the constant current source 120, and its source is grounded. The n-channel MOS transistor 2 outputs a constant current generated by the constant current source 120. The source of the p-channel MOS transistor 5 is connected to the power source, and its gate is connected to the drain and gate of the p-channel MOS transistor 7. [

The switching-off circuit 121 is formed of a p-channel MOS transistor 11 serving as a constant current device and a p-channel MOS transistor 9 serving as a switching device. The source of the p-channel MOS transistor 11 is connected to the power source, and its gate is connected to the constant current source 120. The gate of the p-channel MOS transistor 9 receives the output from the inverter 17 and its source and drain are connected to the drain of the p-channel MOS transistor 11 and to the gate of the p- do.

The source of the p-channel MOS transistor 7 is connected to the power supply, and the drain thereof is connected to the loop filter 23. The p-channel MOS transistor 7 together with the p-channel MOS transistor 5 forms a current mirror circuit.

The gate of the p-channel MOS transistor 4 receives the output from the inverter 18 and its drain and source are connected to the drain of the n-channel MOS transistor 6 and the drain of the p-channel MOS transistor 3, respectively do. When the phase error / down signal 102 is activated (high level), the p-channel MOS transistor 4 is turned on and the current determined by the p-channel MOS transistor 3 flows through the source and the drain. A series circuit composed of two MOS transistors 3 and 4 forms a constant current switching circuit.

The gate of the p-channel MOS transistor 3 is connected to the constant current source 120, and its source is grounded. The p-channel MOS transistor 3 outputs a constant current generated by the constant current source 120. The source of the n-channel MOS transistor 6 is grounded, and its gate is connected to the drain and gate of the n-channel MOS transistor 8.

The switching-off circuit 122 is formed of a p-channel MOS transistor 12 serving as a constant current device and an n-channel MOS transistor 10 serving as a switching device. The source of the n-channel MOS transistor 12 is connected to the power source, and the gate thereof is connected to the constant current source 120. The gate of the n-channel MOS transistor 10 receives the output from the inverter 18 and its source and drain are connected to the drain of the n-channel MOS transistor 12 and the gate of the n- do.

The source of the n-channel MOS transistor 8 is connected to the power supply, and the drain thereof is connected to the loop filter 123 together with the drain of the p-channel MOS transistor 7. The n-channel MOS transistor 8 together with the n-channel MOS transistor 6 forms a current mirror circuit.

The operation of the charge pumping circuit having such a configuration will be described.

First, the operation of the phase error / up signal 101 which is active (low level) will be described. When the phase error / up signal 101 changes to low level and the output from the inverter 17 changes to high level, the n-channel MOS transistor 1 is turned on and the n-channel MOS transistor 2 A predetermined current flows through the p-channel MOS transistor 5. The p-channel MOS transistors 5 and 7 form a current mirror circuit. Therefore, the charge current I _up having a current value based on the current flowing through the source and the drain of the p-channel MOS transistor 5 flows through the source and the drain of the p-channel MOS transistor 7 and is supplied to the loop filter 123 .

When the phase error / up signal 101 changes from the active state (low level) to the inactive state (high level) and the output from the inverter 17 changes from the high level to the low level, the p-channel MOS transistor 9 is immediately turned on. Thereby, the gate of the p-channel MOS transistor 7 is charged by the current determined by the p-channel MOS transistor 11, and the p-channel MOS transistor 7 is turned off.

In this way, the current is controlled by the turn-off of the p-channel MOS transistor 7. This can shorten the time (turn-off time) required to turn off the p-channel MOS transistor 7 after the phase error / up signal 101 becomes inactive.

The operation of the active (high level) phase error / down signal 102 will be described. When the phase error / down signal 102 changes to a high level and the output from the inverter 18 changes to a low level, the p-channel MOS transistor 4 is turned on and turned on by the p-channel MOS transistor 3 A predetermined current flows through the n-channel MOS transistor 6. The n-channel MOS transistors 6 and 7 form a current mirror circuit. Therefore, a discharge current I _Down having a current value based on the current flowing through the source and the drain of the n-channel MOS transistor 6 flows through the source and the drain of the n-channel MOS transistor 8 and flows through the loop filter 123 Discharge.

When the phase error / down signal 102 changes from a high level to a low level and the output from the inverter 18 changes from a low level to a high level, the n-channel MOS transistor 10 of the switching- Is immediately turned on. Thereby, the gate of the n-channel MOS transistor 8 is discharged by the current determined by the n-channel MOS transistor 12, and the n-channel MOS transistor 8 is turned off.

In this way, the current is controlled by turning off the n-channel MOS transistor 8. This makes it possible to shorten the time (turn-off time) required to turn off the n-channel MOS transistor 8 after the phase error / down signal 102 is made inactive.

In the first embodiment, since the constant current output voltage V _GS between the gate and the source of each MOS transistor 7 or 8 is not affected by the switching operation, the output constant current hardly fluctuates due to the switching operation, .

Simulation by a computer using the charge pumping circuit of the first embodiment showed that the reference leakage was reduced by about 15 dB from the reference leakage in the conventional charge pumping circuit shown in FIG.

In the first embodiment, the p-channel and n-channel MOS transistors 7 and 8 are controlled as power switches without providing any switching circuit and any constant current source on the output stage. The charge current I _up and the discharge current I _Down as the output current have a constant gain irrespective of the output state.

The switching-off circuits 121 and 122, which are turned on for the inactive phase error signal to charge and discharge the gate, respectively, can shorten the turn-off time of the p-channel and n-channel MOS transistors 7 and 8 . Thus, the output current linearity with respect to the phase error signal can be improved.

The charge pumping circuit of the first embodiment can maintain good output current linearity for the phase error signal, thereby reducing reference leakage. Since the phase error signal is received by the MOS transistor, the charge pumping circuit does not require any particular circuit for connection to a digital phase comparator operating in TTL logic.

(Second Embodiment)

Fig. 2 shows a charge pumping circuit according to a second embodiment of the present invention.

In the second embodiment, the switching-off circuits 121 and 122 of the first embodiment shown in Fig. 1 are replaced by the switching-off circuits 131 and 132. In Fig.

Unlike the switching-off circuit 121, the switching-off circuit 131 does not use the p-channel MOS transistor 11 but consists only of the p-channel MOS transistor 9. Unlike the switching-off circuit 122, the switching-off circuit 132 does not use the p-channel MOS transistor 12 but consists only of the n-channel MOS transistor 10.

In the second embodiment, since the switching-off circuits 131 and 132 do not include any MOS transistor serving as a constant current source, when the p-channel and n-channel MOS transistors 7 and 8 are turned off Switching noise may be superimposed on the gate. However, the second embodiment has the effect of constituting the switching-off circuits 131 and 132 with a small number of elements in addition to the effect of the first embodiment. The charge pumping circuit can be used in negligible switching noise.

The first and second embodiments are applied to the charge pumping circuit 72 of the PLL frequency synthesizer shown in FIG. 3, and operate in the above-described manner. It should be noted that the description of the phase comparator 71, the loop filter 23, the voltage-controlled oscillator 73, and the frequency divider 74 will be omitted.

INDUSTRIAL APPLICABILITY As described above, the present invention exhibits the following effects.

(1) The reference leakage can be reduced since V _GS in the output MOS transistor for generating the charging or discharging current is not affected by the switching operation.

(2) Since the gain and charge and discharge current as the output current are constant regardless of the output state of the control voltage, a stable stabilization time can be realized.

(3) Since a switching-off circuit is provided, good output current linearity can be maintained for the phase error signal, thereby reducing reference leakage.

(4) Since the switching transistor for receiving the phase error signal is a MOS transistor, it is possible to reduce the scale of the circuit without requiring any specific circuit for connection with the digital phase comparator.

Claims (10)

In a charge pumping circuit, A constant current source 120 for generating and outputting a current having a constant current value, Switch means (1, 2; 3, 4) for turning on when the input signal is active and outputting a current determined by the constant current source; First MOS transistors (5, 6) through which the current outputted from the switch means flows, Second MOS transistors (7, 8) for forming a current mirror circuit together with the first MOS transistor and outputting a current having a current value based on a current flowing through the first MOS transistor as one of a charge current and a discharge current, Wow, Off means (121, 122; 131, 132) for turning off the second MOS transistor by charging or discharging the gate of the second MOS transistor when the input signal is inactive, ≪ / RTI > 2. The apparatus of claim 1, wherein the switching- A constant current element (11, 12) for generating a current having a constant current value based on a current from the constant current source, Switching elements (9, 10) which are turned on when the input signal is inactive and output a current generated by the constant current element to the gate of the second MOS transistor, ≪ / RTI > The charge pumping circuit according to claim 2, wherein the constant current element and the switching element are formed by third and fourth MOS transistors, respectively. 2. The apparatus of claim 1, wherein the switching- A switching element (9, 10) which is turned on when the input signal is inactive and outputs a current to the gate of the second MOS transistor, ≪ / RTI > The charge pumping circuit according to claim 4, wherein the switching element is formed of a third MOS transistor. 2. The apparatus of claim 1, wherein the switch means A third MOS transistor (2, 3) for generating a current having a constant current value based on the current from the constant current source, Fourth MOS transistors (1, 4) that are turned on when the phase error signal is inactive and supply the current generated by the third MOS transistor to the first MOS transistor and the switching- ≪ / RTI > The method according to claim 6, The gates of the first and second MOS transistors are connected to each other, Wherein the switching-off means is connected between a gate of the first MOS transistor and a power source, And a drain of the fourth MOS transistor is connected to a drain and a gate of the first MOS transistor Charge pump circuit. A PLL frequency synthesizer comprising: And outputs a phase error / up signal when the phase of the comparison signal is delayed relative to the phase of the reference signal, and outputs a phase error / up signal when the phase of the comparison signal is ahead of the phase of the reference signal. A phase comparator 71 for outputting an error / down signal, A charge pumping circuit (72) for outputting a charge current and a discharge current based on a phase error / up signal and a phase error / down signal from the phase comparator, A loop filter (23) for generating a control voltage based on the charge current and the discharge current output from the charge pumping circuit, A voltage controlled oscillator (73) for outputting a signal whose frequency is controlled by a control voltage from the loop filter (23) as an oscillation output signal, A frequency divider (74) for outputting a comparison signal obtained by dividing the frequency of the oscillation output signal from the voltage controlled oscillator to the charge pumping circuit, Lt; / RTI > The charge pumping circuit A constant current source 120 for generating and outputting a current having a constant current value, Switch means (1, 2; 3, 4) for turning on when the phase error / up signal and the phase error / down signal are active and outputting a current determined by the constant current source; First MOS transistors (5, 6) through which the current outputted from the switch means flows, Second MOS transistors (7, 8) for forming a current mirror circuit together with the first MOS transistor and outputting a current having a current value based on a current flowing through the first MOS transistor as one of a charge current and a discharge current, Wow, Off means (121, 122) for turning off the second MOS transistor by charging or discharging the gate of the second MOS transistor when the phase error / up signal and the phase error / down signal are inactive, And a PLL frequency synthesizer. 9. The apparatus of claim 8, wherein the switching- A constant current element (11, 12) for generating a current having a constant current value based on a current from the constant current source, (9, 10) for turning on when the phase error / up signal and phase error / down signal are inactive and outputting a current generated by the constant current device to the gate of the second MOS transistor, And a PLL frequency synthesizer. 10. The semiconductor memory device according to claim 8, further comprising switching elements (9, 10) that are turned on when the phase error / up signal and phase error / down signal are inactive and output a current to the gate of the second MOS transistor, And a PLL frequency synthesizer.