JP2002330067A - Charge pump circuit and phase synchronizing loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump circuit and a phase synchronizing loop circuit capable of effectively reducing overshoot currents to be superimposed on input and output currents. SOLUTION: A p-type MOS transistor 22a and a p-type MOS transistor 22b are constituted so that the rate of the channel length to the width can be the same, and drain currents approximating to the same gate voltage are allowed to run. When a signal UP is turned into a high level, the p-type MOS transistor 22b is conducted in a saturated state, and the p-type MOS transistor 22a is turned into a non-conductive state. When the signal UP is turned into a low level, the p-type MOS transistor 22a is conducted, and the p-type MOS transistor 22b is turned into the non-conductive state. In any case, the source potentials of the p-type MOS transistor 22a and the p-type MOS transistor 22b are fixed, and any parasitic capacity in parallel with a constant current circuit 21 is not charged or discharged. In the same way, any parasitic capacity in parallel with a constant current circuit 23 is not charged or discharged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit and a phase locked loop circuit including the same.
The present invention relates to a charge pump circuit configured on a semiconductor integrated circuit and a phase locked loop circuit including the same.

[0002]

2. Description of the Related Art Phase Locked Loop (Phase Locked Loo)
A p circuit (PLL circuit) is a circuit that can obtain an output signal whose phase and frequency are synchronized with an input signal, and is used for various circuits that perform frequency control, such as a clock multiplication circuit, a clock reproduction circuit, and a frequency synthesizer. I have.

A general PLL circuit has a configuration in which a phase frequency comparator, a charge pump circuit, a low-pass filter, a voltage controlled oscillator (VCO), and a frequency divider are connected in a loop. .

In the phase frequency comparator, a phase difference and a frequency difference between an input signal and a feedback signal are compared, and an input / output current corresponding to the comparison result is generated by a charge pump circuit and supplied to a low-pass filter. The capacitor of the low-pass filter is charged and discharged by this input / output current to generate a smoothed voltage. When the frequency of the output signal of the VCO changes according to the smoothed voltage, the frequency of the feedback signal obtained by dividing the output signal by the frequency divider also changes. When the phase of the feedback signal is delayed with respect to the input signal, the input / output current of the charge pump circuit is adjusted in a direction to increase the frequency of the feedback signal, whereby the output voltage of the low-pass filter changes and the output signal of the VCO And the frequency of the feedback signal increases. vice versa,
When the phase of the feedback signal is advanced with respect to the input signal, the input / output current of the charge pump circuit is adjusted in a direction to lower the frequency of the feedback signal. In this way, the phase and frequency of the feedback signal are controlled so that the phase is synchronized with the input signal.

[0005]

Incidentally, the conventional charge pump circuit has a problem that overshoot occurs in the input / output current due to the parasitic capacitance of the circuit. Hereinafter, to explain this problem, a conventional charge pump circuit will be described with reference to FIG. FIG. 12 is a circuit diagram showing an example of a conventional charge pump circuit. FIG.
The charge pump circuit shown in FIG.
OS transistor 2, constant current circuit 3, and n-type MOS
It has the transistor 4 and the parasitic capacitance C1 of the circuit.
And parasitic capacitance C2.

[0006] The constant current circuit 1 allows a constant current I1 to flow from the power supply line to the source of the p-type MOS transistor. Further, a parasitic capacitance C1 is generated in parallel with the constant current circuit 1. The source of the p-type MOS transistor 2 is the current I1 of the constant current circuit 1, and the drain is the current input / output terminal LP.
F, and inputs the signal UP to the gate. The constant current circuit 3 allows a constant current I2 to flow from the source of the n-type MOS transistor 2 to the ground line. Further, a parasitic capacitance C2 is generated in parallel with the constant current circuit 3. The n-type MOS transistor 4 outputs the current I2 of the constant current circuit 3 from the source, the drain is connected to the current input / output terminal LPF, and the signal DN is input to the gate.

The signal UP and the signal DN are high-level or low-level pulse signals output from the phase frequency comparator. When increasing the output voltage of the low-pass filter, the signal UP is set to a low level. As a result, the p-type MOS transistor 2 conducts, and the current I1 from the constant current circuit 1 is output from the current input / output terminal LPF, and the capacitor of the low-pass filter is charged by this current. Conversely, when lowering the output voltage of the low-pass filter, the signal DN is set to a high level.
As a result, the n-type MOS transistor 4 conducts, and the current I2 is input to the constant current circuit 3 from the current input / output terminal LPF, and this current discharges the capacitor of the low-pass filter. Thus, when increasing the output voltage of the low-pass filter, the p-type MOS transistor 2 conducts, and when decreasing, the n-type MOS transistor 4 conducts, and the capacitor of the low-pass filter is connected from the current input / output terminal LPF. The current to be charged and discharged is input and output.

On the other hand, when these transistors are off, the conductance of the constant current circuit increases because the current is cut off, and the constant current circuit is turned on. For example, when the signal UP goes high and the p-type MOS
When the transistor 2 is turned off, the constant current circuit 1 is turned on. Thereby, the negative charge charged in the parasitic capacitance C1 is discharged by the constant current circuit 1, and
The source voltage of the p-type MOS transistor is the power supply voltage VDD.
Approach.

In this state, when the signal UP goes low and the p-type MOS transistor 2 becomes conductive, the discharged parasitic capacitance C1 is charged with negative charge again, and the voltage across the parasitic capacitance C1 becomes the power supply voltage VDD. And current input / output terminal L
It becomes equal to the potential difference between PF. Since the negative charge for charging the parasitic capacitance C1 is supplied from the capacitor of the low-pass filter via the current input / output terminal LPF, the output current of the current input / output terminal LPF includes the current I1
The current Ip for charging the parasitic capacitance C1 is superimposed as an overshoot current.

Similarly, when the signal DN goes low, n
When the type MOS transistor 4 is turned off, the constant current circuit 3 is turned on. As a result, the positive charge charged in the parasitic capacitance C2 is discharged by the constant current circuit 3, and the source voltage of the n-type MOS transistor 4 approaches the ground voltage.

In this state, when the signal DN goes high and the n-type MOS transistor 4 becomes conductive, the discharged parasitic capacitance C2 is again charged with negative charges, and the voltage across the parasitic capacitance C2 is a current input / output. It is equal to the potential difference between the terminal LPF and the ground line. Since the positive charge for charging the parasitic capacitance C2 is supplied from the capacitor of the low-pass filter via the current input / output terminal LPF, the input current of the current input / output terminal LPF includes the parasitic capacitance to the current I2 of the constant current circuit 3. A current In for charging C2 is superimposed as an overshoot current.

As described above, in the conventional charge pump circuit, in the initial stage when the transistor on the power supply line side or the ground line side becomes conductive and current is input / output from the current input / output terminal LPF, the parasitic capacitance is charged. There is a problem that an overshoot current is generated. When the smoothing voltage of the low-pass filter fluctuates due to such an overshoot current, feedback control works in the PLL circuit to correct the fluctuation, and there is a problem that a frequency jitter in which the frequency of the output signal constantly fluctuates occurs. .

The magnitude of the overshoot current varies depending on the capacitance value of the parasitic capacitance, the voltage level of the current input / output terminal LPF, and the like, so that the output current and the input current usually do not match. Therefore, even if the magnitudes of the currents I1 and I2 match, this difference in the amount of overshoot causes a difference in the average current value between the output current and the input current for the same phase difference. PL
In the L circuit, feedback control works so as to correct this difference, so that there is a problem that a steady phase shift (referred to as phase offset) occurs between the input signal and the feedback signal.

Furthermore, since the magnitude of the overshoot current changes according to the voltage level of the current input / output terminal LPF, the above-described phase offset tends to depend on the voltage level of the current input / output terminal LPF. On the other hand, the characteristics of the oscillation frequency with respect to the input voltage of the VCO tend to fluctuate in accordance with individual variations in the manufacturing process. Therefore, there is a problem that the phase offset greatly varies from individual to individual.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a charge pump circuit capable of effectively reducing an overshoot current component superimposed on an input / output current, and a phase locked loop circuit having the same. To provide.

[0016]

In order to achieve the above object, a charge pump circuit according to a first aspect of the present invention has a current input / output terminal and a constant current flowing from a first potential to an output terminal. A first constant current circuit for controlling, and a first transistor for controlling a conduction current flowing from an output terminal of the first constant current circuit to the current input / output terminal according to a level of a signal input to a control terminal And a second transistor for controlling a conduction current flowing from an output terminal of the first constant current circuit to a second potential lower than the first potential according to a level of a signal input to the control terminal; In response to the input first control signal, a first-level signal that turns on the first transistor is input to a control terminal of the first transistor, and the second transistor is turned off. Status The second level of the signal becomes a first state in which input to the control terminal of the second transistor,
A first state for inputting the signal of the second level to a control terminal of the first transistor and a second state for inputting the signal of the first level to a control terminal of the second transistor; A continuity control circuit, a second constant current circuit for controlling a current flowing from the input terminal to the second potential to be constant, and a second constant current circuit for controlling the current flowing from the current input / output terminal to the second A third transistor for controlling a conduction current flowing to an input terminal of the second constant current circuit, and an input terminal of the second constant current circuit from the first potential according to a level of a signal input to the control terminal. A fourth transistor for controlling a conduction current flowing through the third transistor, and a third level signal for turning on the third transistor in response to a second control signal inputted thereto, the control terminal of the third transistor A third state in which a fourth level signal that causes the fourth transistor to be in a non-conducting state is input to a control terminal of the fourth transistor; And inputting the signal of the third level to the control terminal of the fourth transistor.
And a second conduction control circuit for switching between the states.

According to the charge pump circuit of the present invention, in the first state, the first level signal is input to the control terminal of the first transistor, and
Is turned on, the signal of the second level is input to the control terminal of the second transistor, and the second transistor is turned off. Accordingly, the output current from the first constant current circuit conducts the first transistor and flows to the current input / output terminal. In the second state, the second state
Is input to the control terminal of the first transistor, the first transistor is turned off, and the signal of the first level is input to the control terminal of the second transistor. Thus, the second transistor is turned on. Thus, the output current from the first constant current circuit conducts the second transistor and flows to the second potential. In the third state, the signal of the third level is input to a control terminal of the third transistor, the third transistor is turned on, and the signal of the fourth level is changed to the third level. The signal is input to the control terminal of the fourth transistor, so that the fourth transistor is turned off. Thereby, the third transistor is conducted from the current input / output terminal, and an input current flows to the second constant current circuit. In the fourth state, the signal of the fourth level is input to the control terminal of the third transistor, the third transistor is turned off, and the signal of the third level is turned off. The signal is input to the control terminal of the fourth transistor, and the fourth transistor is turned on.
As a result, the fourth transistor is turned on from the first potential, and an input current flows to the second constant current circuit.

Preferably, when the voltage level of the control terminal is the same, the first transistor and the second transistor have similar conduction currents, and the third transistor and the fourth transistor have the same conduction level. The transistors have similar conduction currents when the control terminal has the same voltage level. In this case, the first transistor and the second transistor may be transistors having an equivalent structure having a form similar to each other, and the third transistor and the fourth transistor may be similar to each other. A transistor having an equivalent structure having the above configuration may be used.

Further, the first conduction control circuit switches the input first-level signal or the input second-level signal in response to the first control signal. The semiconductor device may include a first switch circuit that outputs signals to a control terminal of a first transistor and a control terminal of the second transistor, respectively, and the second conduction control circuit receives an input signal in response to the second control signal. The third
And a second switch circuit for switching the signal of the fourth level or the input signal of the fourth level and outputting the signals to the control terminal of the third transistor and the control terminal of the fourth transistor, respectively. In this case, the first conduction control circuit includes a first voltage generation circuit that generates the first level voltage, and a filter circuit that attenuates a noise component in an output line of the first voltage generation circuit. The second conduction control circuit may include a second voltage generation circuit that generates the second level voltage, and a filter that attenuates a noise component in an output line of the second voltage generation circuit. And a circuit.

Further, the first conduction control circuit includes a fifth transistor and a sixth transistor whose input / output terminals are connected to the first potential, and the first level in the first state. Is input to the control terminal of the fifth transistor, the control terminal of the sixth transistor is connected to the second potential, and in the second state, the signal of the first level is transmitted to the control terminal of the fifth transistor. And a third switch circuit that inputs the control terminal of the fifth transistor to the control terminal of the fifth transistor and connects the control terminal of the fifth transistor to the second potential. And the seventh transistor and the eighth transistor connected to the second potential, and in the third state, inputting the signal of the third level to a control terminal of the seventh transistor, Is connected to the first potential, and in the fourth state, the signal of the third level is input to the control terminal of the eighth transistor, and the control terminal of the seventh transistor is To the first potential.

A phase locked loop circuit according to a second aspect of the present invention compares a phase difference between an input signal and a feedback signal, and outputs a first control signal and a second control signal having a level corresponding to the comparison result. A phase comparison circuit for outputting a signal;
A charge pump circuit that inputs or outputs a current according to the level of the control signal and the second control signal, a smoothing circuit that receives an input / output current of the charge pump circuit, and outputs a smoothed voltage, A phase-locked loop circuit having a voltage-controlled oscillation circuit that generates the feedback signal having a frequency corresponding to the output voltage of the smoothing circuit;
The charge pump circuit includes: a current input / output terminal; a first constant current circuit that controls a current flowing from a first potential to an output terminal to be constant; A first transistor for controlling a conduction current flowing from the output terminal of the first constant current circuit to the current input / output terminal; and an output terminal of the first constant current circuit in accordance with a level of a signal input to the control terminal. A second transistor for controlling a conduction current flowing from the first potential to a second potential lower than the first potential, and a first level at which the first transistor is rendered conductive in response to the first control signal. Inputting a signal to the control terminal of the first transistor;
A first state in which a signal of a second level at which the second transistor is turned off is input to a control terminal of the second transistor, or a signal of the second level is input to the control terminal of the second transistor; A first conduction control circuit for switching a second state of inputting the first level signal to the control terminal of the second transistor while inputting to the control terminal, and flowing from the input terminal to the second potential A second constant current circuit for controlling the current to be constant, and a conduction current flowing from the current input / output terminal to the input terminal of the second constant current circuit in accordance with the level of a signal input to the control terminal. A third transistor, a fourth transistor for controlling a conduction current flowing from the first potential to the input terminal of the second constant current circuit in accordance with a level of a signal input to the control terminal; Depending on the second control signal, the third level of the signal which the third transistor is turned together with the input to the control terminal of the third transistor,
A third state in which a fourth-level signal in which the fourth transistor is turned off is input to a control terminal of the fourth transistor, or a fourth-level signal in which the fourth level signal is input to the control terminal of the fourth transistor; A second conduction control circuit for switching a fourth state of inputting the third-level signal to the control terminal of the fourth transistor while inputting the signal to the control terminal.

Preferably, when the voltage level of the control terminal is the same, the first transistor and the second transistor have similar conduction currents, and the third transistor and the fourth transistor have the same conduction level. The transistors have similar conduction currents when the control terminal has the same voltage level. In this case, the first transistor and the second transistor may be transistors having an equivalent structure and having a form similar to each other, and the third transistor and the fourth transistor may have a form similar to each other. May be a transistor having an equivalent structure.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a schematic block diagram of a PLL circuit according to the present invention. FIG.
Includes a phase frequency comparator 10, a charge pump circuit 20, a low-pass filter 30, a VCO 40,
And a frequency divider 50.

The phase frequency comparator 10 compares the phase and frequency of the input reference clock signal with the output signal of the frequency divider 50, and generates a signal UP and a signal DN having levels according to the comparison result. .

The charge pump circuit 20 inputs and outputs a current to and from the low-pass filter 30 in accordance with the levels of the signal UP and the signal DN of the phase frequency comparator 10. The overshoot current component of the input / output current of the charge pump circuit 20 is suppressed by the circuit of the present invention described later.

The low-pass filter 30 receives the input / output current of the charge pump circuit 20, removes the higher harmonic components, and outputs a smoothed voltage to the VCO 40. For example,
As shown in FIG. 1, the charge pump circuit 20 includes a series circuit of a resistor 31 and a capacitor 32 connected between an output line of the charge pump circuit 20 and a ground line, and a capacitor 33 connected in parallel to the resistor 31 and the capacitor 32. The charge and discharge of the capacitor 32 and the capacitor 33 by the input / output current of the pump circuit 20 generate a smoothed voltage.

The VCO 40 generates a signal having a frequency corresponding to the output voltage of the low-pass filter 30 and outputs the signal to the frequency divider 50. The frequency divider 50 divides the frequency of the output signal of the VCO 40 by a predetermined frequency division ratio and feeds it back to the phase frequency comparator 10.

In the phase frequency comparator 10, the phase difference and the frequency difference between the reference clock signal and the feedback signal from the frequency divider 50 are compared, and the signal UP and the signal DN according to the comparison result are sent to the charge pump circuit 20. Will be entered.
In the charge pump circuit 20, an input / output current corresponding to the signal UP and the signal DN is generated and supplied to the low-pass filter 30. The capacitor of the low-pass filter 30 is charged / discharged by the input / output current to generate a smoothed voltage. V according to the smoothed voltage
When the frequency of the output signal of the CO 40 changes, the frequency of the feedback signal obtained by dividing the output signal by the frequency divider 50 also changes. When the phase of the feedback signal from the frequency divider 50 lags behind the reference clock signal, the input / output current of the charge pump circuit 20 is adjusted in a direction to increase the frequency of the feedback signal. The voltage changes, the frequency of the output signal of the VCO 40 changes, and the frequency of the feedback signal increases. Conversely, when the phase of the feedback signal is advanced with respect to the input signal, the input / output current of the charge pump circuit 20 is adjusted so as to decrease the frequency of the feedback signal. Thus, in the PLL circuit of FIG. 1, the phase and frequency of the feedback signal are controlled so that the phase is synchronized with the reference clock signal.

Next, the charge pump circuit 20 of the PLL circuit shown in FIG. 1 will be described. FIG. 2 shows the first embodiment of the present invention.
FIG. 4 is a schematic circuit diagram of a charge pump circuit according to the embodiment. The charge pump circuit shown in FIG. 2 includes a constant current circuit 21, a constant current circuit 23, a p-type MOS transistor 22
a, a p-type MOS transistor 22b, an n-type MOS transistor 24a, an n-type MOS transistor 24b, a switch circuit 25, a switch circuit 27, a voltage generation circuit 26, and a voltage generation circuit 28.

The p-type MOS transistor 22a and the p-type MOS transistor 22b have their sources connected to a power supply line via a constant current circuit 21 and their gates connected via a switch circuit 25 to a power supply line or a voltage generation circuit 26.
Are connected to the output line N26. The drain of the p-type MOS transistor 22a is connected to the current input / output terminal LPF, and the drain of the p-type MOS transistor 22b is connected to the ground line. The sources of the n-type MOS transistor 24a and the n-type MOS transistor 24b are connected to the ground line via the constant current circuit 23, and the gate is connected to the ground line or the output line N28 of the voltage generation circuit 28 via the switch circuit 27. Connected respectively. The drain of the n-type MOS transistor 24a is connected to the current input / output terminal LPF, and the drain of the n-type MOS transistor 24b is connected to the power supply line.

The switch circuit 25 includes the phase frequency comparator 1
The gates of the p-type MOS transistor 22a and the p-type MOS transistor 22b are connected to the power supply line or the output line N2 of the voltage generation circuit 26 according to the level of the signal UP of 0.
6 are switches connected to any one of the switches. In the following description, as an example, when the signal UP is at a high level, p
The gate of the p-type MOS transistor 22a is connected to a power supply line, p
The gate of the MOS transistor 22b is connected to the voltage generation circuit 2
6 are connected to the output lines N26, respectively, and when the signal UP is at the low level, they are connected in reverse.

Similarly, the switch circuit 27 switches the n-type MOS transistor 24a and the n-type MOS transistor 24b in accordance with the level of the signal DN of the phase frequency comparator 10.
Are connected to either the ground line or the output line N28 of the voltage generation circuit 28. In the following description, as an example, when the signal DN is at a high level, the gate of the n-type MOS transistor 24a is connected to the output line N28 of the voltage generation circuit 28, and the gate of the n-type MOS transistor 24b is connected to the ground line. At the low level, they are connected in reverse.

The p-type MOS transistor 22a and the p-type MOS transistor 22b are preferably transistors that pass similar source-drain currents when the same voltage is applied to the gates. Therefore, it is preferable that these transistors be transistors having an equivalent structure having a form similar to each other. For example, the channels are formed to have substantially the same length and width, and are arranged adjacently on the same semiconductor chip.

Similarly, the n-type MOS transistor 24a and the n-type MOS transistor 24b preferably have a source-approximation approximating when the same voltage is applied to the gate.
This is a transistor that allows a drain current to flow. Therefore,
These transistors are also preferably transistors having an equivalent structure having a form similar to each other. For example, the transistors are formed so that the length and width of the channel are substantially equal, and are arranged adjacently on the same semiconductor chip. .

The voltage generation circuit 26 generates a gate voltage V1 at which the p-type MOS transistor 22a and the p-type MOS transistor 22b are saturated and turned on, and supplies the gate voltage V1 to the gates of these transistors via the switch circuit 25. I do. Therefore, voltage V1 is set such that the current conduction capability of these transistors is higher than output current I1 of constant current circuit 21.

Similarly, the voltage generation circuit 28 is an n-type MOS
Transistor 24a and n-type MOS transistor 24
b generates a gate voltage V2 that saturates and becomes conductive,
The signals are supplied to the gates of these transistors via the switch circuit 27. Therefore, voltage V2 is set such that the current conduction capability of these transistors is higher than input current I2 of constant current circuit 23.

Here, the operation of the charge pump circuit of FIG. 2 having the above configuration will be described. First, the operation of the charge pump circuit according to the level of the signal UP will be described. When the signal UP is at a high level, the p-type MOS transistor 2
Since the power supply voltage VDD is applied to the gate of 2a and the voltage V1 is applied to the gate of the p-type MOS transistor 22b via the switch circuit 25, the p-type MOS transistor 22a is in a non-conductive state and the p-type MOS transistor 22b
Becomes conductive. Therefore, the current I1 of the constant current circuit 21 flows to the ground line via the p-type MOS transistor 22b, and does not flow to the p-type MOS transistor 22a. When the signal UP is at the low level, on the contrary, the current input / output terminal LP is connected via the p-type MOS transistor 22a.
The current I1 flows through F and does not flow through the p-type MOS transistor 22b. Therefore, the current I1 of the constant current circuit 21
Flows into one of the p-type MOS transistor 22a and the p-type MOS transistor 22b according to the level of the signal UP.

When the p-type MOS transistor 22a and the p-type MOS transistor 22b are conducting, the gate voltage is equal to the voltage V1. Since these transistors are operating in a saturated state, the source-drain current is almost equal to the current I1. Becomes equal to Further, if these transistors are transistors having an equivalent structure having a form similar to each other, the gate-source voltage for the same source-drain current becomes substantially equal. Therefore, p
The source potentials of the type MOS transistor 22a and the p-type MOS transistor 22b are substantially equal regardless of whether the signal UP is at a high level or a low level.
As a result, the voltage of the parasitic capacitance generated in parallel with the constant current circuit 21 becomes substantially constant irrespective of the level of the signal UP, and charging and discharging of the electric charge in the parasitic capacitance is suppressed. That is,
The overshoot current component superimposed on the current output from the current input / output terminal LPF to the low-pass filter 30 is reduced.

Next, the operation of the charge pump circuit according to the level of signal DN will be described. When the signal DN is at a high level, the voltage V2 is applied to the gate of the n-type MOS transistor 24a and the ground voltage is applied to the gate of the n-type MOS transistor 24b via the switch circuit 27. Conducted state, n-type M
The OS transistor 24b is turned off. Therefore, the current I2 of the constant current circuit 23 is
F flows into the constant current circuit 23 via the n-type MOS transistor 24a, and does not flow to the n-type MOS transistor 24b. When the signal UP is at the low level, on the contrary, the n-type MOS transistor 24 is connected to the power supply line VDD.
The current I2 flows into the constant current circuit 23 via the line b, and does not flow to the n-type MOS transistor 24a. Therefore,
The current I2 of the constant current circuit 23 flows to one of the n-type MOS transistor 24a and the n-type MOS transistor 24b according to the level of the signal DN.

When the n-type MOS transistor 24a and the n-type MOS transistor 24b are conducting, the gate voltage is equal to the voltage V2, and since these transistors operate in the saturation state, the source-drain current is almost equal to the current I2. Becomes equal to Further, if these transistors are transistors having an equivalent structure having a form similar to each other, the gate-source voltage for the same source-drain current becomes substantially equal. Therefore, n
The source potentials of the type MOS transistor 24a and the n-type MOS transistor 24b are substantially equal regardless of whether the signal DN is at a high level or a low level.
As a result, the voltage of the parasitic capacitance generated in parallel with the constant current circuit 23 becomes substantially constant irrespective of the level of the signal DN, and charging and discharging of the electric charge in the parasitic capacitance is suppressed. That is,
The overshoot current component superimposed on the current input from the low-pass filter 30 to the current input / output terminal LPF is reduced.

As described above, according to the charge pump circuit shown in FIG. 2, the p-type M
Even if one of the OS transistor 22a and the p-type MOS transistor 22b is turned on, the source potential of these transistors is substantially constant. Similarly, according to the level of signal DN, n-type MOS transistor 24a
Even if one of the n-type MOS transistor 24b and the n-type MOS transistor 24b is turned on, the source potential of these transistors is also substantially constant. Therefore, the overshoot current component superimposed on the input / output current of the charge pump circuit can be effectively reduced.

Further, since the current component due to overshoot contained in the average current of the input current and the output current of the charge pump circuit is reduced, the average current of the input current and the output current can be adjusted effectively. The imbalance of these average currents can be reduced. Thereby, a steady phase offset can be reduced.

When current is input / output,
Since the p-type MOS transistor 22a and the n-type MOS transistor 24a are turned on, the current input / output terminal LPF
Is controlled by a constant current circuit 21 or a constant current circuit 23 to a constant current. Thus, the magnitude of the input / output current can be made constant without being affected by the voltage of the low-pass filter 30.

The constant current circuit 21 and the constant current circuit 2
In FIG. 3, a constant current always flows regardless of whether an input / output current flows through the current input / output terminal LPF.
Unlike the conventional circuit shown in FIG. 2, the current of the constant current circuit is not interrupted. Therefore, since the response time of the constant current circuit until the interrupted current rises to the constant current again is shortened, the rise of the input / output current can be made faster than before, and the PLL circuit can be operated at a higher frequency. Can be.

<Second Embodiment> Next, a second embodiment of the present invention will be described. In the second embodiment, the charge pump circuit of FIG.
It is a more concrete embodiment.

FIG. 3 is a schematic circuit diagram of a charge pump circuit according to a second embodiment of the present invention. The charge pump circuit shown in FIG.
3, p-type MOS transistor 22a, p-type MOS transistor 22b, n-type MOS transistor 24a, n-type M
OS transistor 24b, switch circuit 25, switch circuit 27, voltage generation circuit 26, and voltage generation circuit 28
Having. The same reference numerals in FIGS. 2 and 3 indicate components having the same function.

The constant current circuit 21 has a p-type MOS transistor 21a and a p-type MOS transistor 21b whose sources are connected to the power supply line and whose gates are connected to each other, and between the drain of the p-type MOS transistor 21b and the ground line. Is connected to the constant current circuit 21c.
The drain of the p-type MOS transistor 21a is
S transistor 22a and p-type MOS transistor 2
2b, the p-type MOS transistor 21
The drain of b is connected to its own gate. In the constant current circuit 21 having such a configuration, since the p-type MOS transistor 21a and the p-type MOS transistor 21b form a current mirror circuit, a current equivalent to the current I of the constant current circuit 21c is applied to the p-type MOS transistor 21a. Output from the drain.

The constant current circuit 23 has an n-type MOS transistor 23a and an n-type MOS transistor 23b whose sources are connected to the ground line and whose gates are connected to each other. Is connected to the constant current circuit 23c.
The drain of the n-type MOS transistor 23a is
S transistor 24a and n-type MOS transistor 2
4b, the n-type MOS transistor 23
The drain of b is connected to its own gate. In the constant current circuit 23 having such a configuration, since the n-type MOS transistor 23a and the n-type MOS transistor 23b form a current mirror circuit, a current equivalent to the current I of the constant current circuit 23c is applied to the n-type MOS transistor 23a. Output from the drain.

The switch circuit 25 includes a CMOS switch 25b and a CMOS switch 25d which are a parallel circuit of a p-type MOS transistor and an n-type MOS transistor whose drain and source are connected to each other, and a p-type MOS transistor 25a and a p-type MOS transistor. Transistor 25c
And The CMOS switch 25b has one terminal connected to the output line N26 of the voltage generation circuit 26 and the other terminal connected to the gate of the p-type MOS transistor 22b.
The CMOS switch 25d has one terminal connected to the output line N26 of the voltage generation circuit 26 and the other terminal connected to the gate of the p-type MOS transistor 22a. The p-type MOS transistor 25a has a source connected to the power supply line,
The drain is connected to the gate of the p-type MOS transistor 22b. The p-type MOS transistor 25c has a source connected to the power supply line and a drain connected to the gate of the p-type MOS transistor 22a. Also, the n-type MO of the p-type MOS transistor 25a and the CMOS switch 25b
The signal UP is input to the gate of the S transistor and the p-type MOS transistor of the CMOS switch 25d. The p-type MOS transistor 25c, the p-type MOS transistor of the CMOS switch 25b, and the n-type MOS transistor of the CMOS switch 25d have a gate to which a signal / UP, which is an inverted signal of the signal UP, is input.

In switch circuit 25 having such a configuration, when signal UP is at a high level, CMOS switch 25b and p-type MOS transistor 25c are turned on, and CMOS switch 25d and p-type MOS transistor 25a are turned off. Becomes In this case, the gate of the p-type MOS transistor 22a is connected to the power supply line, and the gate of the p-type MOS transistor 22b is connected to the output line N26 of the voltage generation circuit 26. When the signal UP is at a low level, the CMOS switch 25
The b and p-type MOS transistors 25c are turned off, and the CMOS switch 25d and the p-type MOS transistor 25a are turned on. In this case, the p-type MOS
The gate of the transistor 22a is connected to the output line N26 of the voltage generation circuit 26, and the p-type MOS transistor 22
The gate of b is connected to the power supply line.

The switch circuit 27 includes a CMOS switch 2
7b, a CMOS switch 27d, an n-type MOS transistor 27a, and an n-type MOS transistor 27c. The CMOS switch 27b has one terminal connected to the output line N28 of the voltage generation circuit 28 and the other terminal connected to the n-type
Connected to the gate of S transistor 24a. CMOS
The switch 27d has one terminal connected to the output line N28 of the voltage generation circuit 28, and the other terminal connected to the gate of the n-type MOS transistor 24b. The n-type MOS transistor 27a has a source connected to the ground line and a drain connected to the gate of the n-type MOS transistor 24a. The n-type MOS transistor 27c has a source connected to the ground line and a drain connected to the n-type MOS transistor 2c.
4b is connected to the gate. Further, the n-type MOS transistor 27c, the n-type MOS transistor of the CMOS switch 27b, and the p-type MOS of the CMOS switch 27d
The signal DN is input to the gate of the transistor. n-type MOS transistor 27a, p-type MOS transistor of CMOS switch 27b, and CMOS switch 27
The gate signal / DN which is an inverted signal of the signal DN is input to the n-type MOS transistor d.

In the switch circuit 27 having such a configuration, when the signal DN is at a high level, the CMOS switch 27b and the n-type MOS transistor 27c are turned on, and the CMOS switch 27d and the n-type MOS transistor 27a are turned off. Becomes In this case, the gate of the n-type MOS transistor 24a is connected to the voltage generation circuit 28
And the gate of the n-type MOS transistor 24b is connected to the ground line. When the signal DN is at a low level, the CMOS switch 27
The b and n-type MOS transistors 27c are turned off, and the CMOS switch 27d and the n-type MOS transistor 27a are turned on. In this case, n-type MOS
The gate of the transistor 24a is connected to the ground line,
The gate of the n-type MOS transistor 24b is connected to the output line N28 of the voltage generation circuit 28.

The voltage generation circuit 26 has a source connected to the power supply line, a drain and a gate connected to the output line N26, a p-type MOS transistor 26a, and a constant connection connected between the output line N26 and the ground line. It has a current circuit 26b. Since the gate-source voltage of the p-type MOS transistor 26a is set to a voltage corresponding to the current of the constant current circuit 26b, the voltage of the output line N26 is set according to the constant current value of the constant current circuit 26b. The current value of the constant current circuit 26b is the p-type MOS transistor 2
The current capability of the 2a and p-type MOS transistors 22b is set to be equal to or more than the current value of the constant current circuit 21, and the transistors are set to be saturated reliably.

For example, the p-type MOS transistor 21a,
p-type MOS transistor 21b, p-type MOS transistor 22a, p-type MOS transistor 22b and p-type M transistor
When the OS transistor 26a is a transistor having the same performance, the current value of the constant current circuit 26b is set to about four times the current value of the constant current circuit 21c. Thereby, the p-type MOS transistor 22a and the p-type MO
The current capability of S transistor 22b is set to be equal to or greater than the current value of constant current circuit 21.

The voltage generation circuit 28 has an n-type MOS transistor 28a having a source connected to the ground line, a drain and a gate connected to the output line N28, and a constant connection between the output line N28 and the power supply line. It has a current circuit 28b. Since the gate-source voltage of the n-type MOS transistor 28a is set to a voltage corresponding to the current of the constant current circuit 28b, the voltage of the output line N28 is set according to the constant current value of the constant current circuit 28b. The current value of the constant current circuit 28b is the n-type MOS transistor 2
The current capacity of the 4a and n-type MOS transistors 24b is set to be equal to or greater than the current value of the constant current circuit 23, and these transistors are set to be saturated reliably.

For example, the n-type MOS transistor 23a,
n-type MOS transistor 23b, n-type MOS transistor 24a, n-type MOS transistor 24b and n-type M transistor
When the OS transistor 28a is a transistor having the same performance, the current value of the constant current circuit 28b is set to be about four times the current value of the constant current circuit 23c. Thereby, n-type MOS transistor 24a and n-type MO
The current capability of S transistor 24b is set to be equal to or greater than the current value of constant current circuit 23.

Next, the charge pump circuit of FIG. 3 having the above-described configuration will be described. First, the operation of the charge pump circuit according to the level of the signal UP will be described. When the signal UP is at a high level, the p-type MOS transistor 22
The gate of a is connected to a power supply line via a p-type MOS transistor 25c,
Is connected to the output line N26 of the voltage generation circuit 26 via the CMOS switch 25b. As a result, the p-type MOS transistor 22a is turned off, and the p-type MOS transistor 22b is turned on.
Does not flow to

When the signal UP is at the low level, the p-type MOS
The gate of the transistor 22a is connected to the CMOS switch 25
The gate of the p-type MOS transistor 22b is connected to the power supply line via the p-type MOS transistor 25a. As a result, the p-type MOS transistor 22a is turned on and the p-type MOS transistor 22b is turned off, so that the current of the constant current circuit 21 flows to the current input / output terminal LPF via the p-type MOS transistor 22a, It does not flow to the MOS transistor 22b. in this way,
The current of the constant current circuit 21 is p depending on the level of the signal UP.
It flows to either the type MOS transistor 22a or the p-type MOS transistor 22b.

Therefore, the voltage of the parasitic capacitance generated in parallel with the constant current circuit 21 becomes almost constant irrespective of the level of the signal UP, and charging and discharging of the electric charge in the parasitic capacitance is suppressed. That is, the overshoot current component superimposed on the current output from the current input / output terminal LPF to the low-pass filter 30 is reduced.

Next, the operation of the charge pump circuit according to the level of signal DN will be described. When the signal DN is at the high level, the gate of the n-type MOS transistor 24a is connected to the CM
The n-type MOS transistor 24b is connected to the output line N28 of the voltage generation circuit 28 via the OS switch 27b.
Is connected to a ground line via an n-type MOS transistor 27c. As a result, the n-type MOS transistor 24a becomes conductive and the n-type MOS transistor 24
Since b is in a non-conductive state, the current of the constant current circuit 23 is
From the current input / output terminal LPF to the n-type MOS transistor 24
The current flows into the constant current circuit 23 via a and does not flow to the n-type MOS transistor 24b.

When the signal UP is at a low level, the n-type MOS
The gate of the transistor 24a is connected to a ground line via an n-type MOS transistor 27a, and the gate of the n-type MOS transistor 24b is connected to a CMOS switch 27d.
To the output line N28 of the voltage generation circuit 28. As a result, the n-type MOS transistor 24a is turned off, and the n-type MOS transistor 24b is turned on.
Flows into the constant current circuit 23 via the n-type MOS transistor 24b and does not flow to the n-type MOS transistor 24a. Thus, the current of the constant current circuit 23 is equal to the signal D
The current flows to either the n-type MOS transistor 24a or the n-type MOS transistor 24b according to the level of N.

Therefore, the voltage of the parasitic capacitance generated in parallel with the constant current circuit 23 becomes almost constant irrespective of the level of the signal DN, and the charge and discharge of the electric charge in the parasitic capacitance are suppressed. That is, the overshoot current component superimposed on the current input from the low-pass filter 30 to the current input / output terminal LPF is reduced.

As described above, in the charge pump circuit shown in FIG. 3, similarly to the charge pump circuit shown in FIG. 2, the overshoot current component superimposed on the input / output current can be effectively reduced. .

<Third Embodiment> Next, a third embodiment of the present invention will be described. The third embodiment is different from the charge pump circuit shown in FIG.
The fifth embodiment is characterized in that the n-type MOS transistor is eliminated from the CMOS switch of the switching circuit 5 and the switch circuit 27, and the remaining p-type MOS transistors function as switches.

FIG. 4 is a schematic circuit diagram of a charge pump circuit according to the third embodiment of the present invention. The same reference numerals in FIGS. 2 and 3 as those in FIGS. 2 and 3 indicate components having the same functions. As can be seen by comparing these, the charge pump circuits shown in FIGS. 3 and 4 have the same configuration except for the following points. That is, in the switch circuit 25 of FIG. 4, the CMOS switch 25 of FIG.
The remaining p-type M from which the n-type MOS transistor of b is deleted
The OS transistor 25e functions as a switch, and the n-type MOS of the CMOS switch 25d in FIG.
The remaining p-type MOS transistor 25f from which the transistor has been removed functions as a switch. In the switch circuit 27, the CMOS switch 27b shown in FIG.
P-type MO from which the n-type MOS transistor of
The S transistor 27e functions as a switch, and the remaining p-type MOS transistor 27f in which the n-type MOS transistor of the CMOS switch 27d in FIG. 3 is deleted functions as a switch.

As described above, the n-type MO of the CMOS switch
Even if the S transistor is deleted, the remaining p
If the source voltage is high enough to make the type MOS transistor conductive, p-type voltage is reduced by the potential difference between the gate and the source.
The type MOS transistor can function as a switch. That is, within the range in which the voltages generated by the voltage generating circuits 26 and 28 satisfy the above-described source voltage condition, the charge pump circuit shown in FIG. 4 can also achieve the same operation as the circuit in FIG. The current component can be effectively reduced. Further, the number of elements constituting the circuit can be reduced as compared with the charge pump circuit of FIG.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described. The fourth embodiment is different from the charge pump circuit shown in FIG.
5 and the switch circuit 27 is characterized in that the p-type MOS transistor is deleted from the CMOS switch and the remaining n-type MOS transistor is made to function as a switch.

FIG. 5 is a schematic circuit diagram of a charge pump circuit according to a fourth embodiment of the present invention. The same reference numerals in FIGS. 2 and 3 as those in FIGS. 2 and 3 indicate components having the same functions. As can be seen by comparing these, the charge pump circuits shown in FIGS. 3 and 5 have the same configuration except for the following points. That is, in the switch circuit 25 of FIG. 5, the CMOS switch 25 of FIG.
The remaining n-type M from which the p-type MOS transistor of b is deleted
The OS transistor 25g functions as a switch, and the p-type MOS of the CMOS switch 25d in FIG.
The remaining n-type MOS transistor 25h from which the transistor has been removed functions as a switch. In the switch circuit 27, the CMOS switch 27b shown in FIG.
N-type MO from which the p-type MOS transistor of
The S transistor 27g functions as a switch, and the remaining n-type MOS transistor 27h in which the p-type MOS transistor of the CMOS switch 27d in FIG. 3 is deleted functions as a switch.

As described above, the p-type MO of the CMOS switch is
Even when the S transistor is deleted, the remaining n
If the source voltage is low enough to make the type MOS transistor conductive, the n-type MOS transistor can function as a switch due to the potential difference between the gate and the source. That is, within the range in which the voltages generated by the voltage generation circuits 26 and 28 satisfy the above-described source voltage condition, the charge pump circuit shown in FIG. 5 can also achieve the same operation as the circuit in FIG. The current component can be effectively reduced. Also,
The number of elements constituting the circuit can be reduced as compared with the charge pump circuit of FIG.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described. The fifth embodiment is characterized in that a filter for attenuating a noise component in an output line of a voltage generation circuit is provided in an output line of the voltage generation circuit.

FIG. 6 is a schematic circuit diagram of a charge pump circuit according to a fifth embodiment of the present invention. The same reference numerals in FIG. 6 as those in FIGS. 2 and 3 indicate components having the same functions. As can be seen by comparing these, the charge pump circuits shown in FIGS. 3 and 6 have the same configuration except for the following points. That is, in the voltage generation circuit 26 of FIG. 6, the capacitor C26 is inserted between the output line N26 and the ground line. Further, in the voltage generation circuit 28 of FIG.
A capacitor C28 is inserted between the capacitor 28 and the ground line.

When the gate voltages of p-type MOS transistor 22a and p-type MOS transistor 22b are varied between power supply voltage VDD and the output voltage of voltage generation circuit 26 in accordance with the level of signal UP, p-type MOS transistor 2
Charge and discharge are performed in the gate-source capacitance of the 2a and p-type MOS transistors 22b. When the gate voltage decreases from the power supply voltage VDD to the output voltage of the voltage generation circuit 26, the current for charging the gate-source capacitance transiently flows from the output line N26 to the ground line via the constant current circuit 26b. This current makes the voltage of the output line N26 fluctuate easily. Capacitor C2
Numeral 6 is for suppressing a voltage fluctuation generated in the output line N26 due to the transient current. When the voltage of the output line N26 is stabilized, the p-type MOS
Transistor 22a and p-type MOS transistor 22
It is possible to prevent the malfunction of switching in b. Similarly, the capacitor C28 is for suppressing the voltage fluctuation occurring in the output line N28, and thereby, the capacitor C28
Switching malfunction in the type MOS transistor 24a and the n-type MOS transistor 24b can be prevented.

The insertion position of the capacitor shown in FIG. 6 is an example, and may be inserted between the output line of the voltage generation circuit and the power supply line. Further, the capacitor may be replaced with an appropriate low-pass filter to attenuate noise-like voltage fluctuation due to a transient current.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described. The sixth embodiment is characterized in that the constant current circuit in the voltage generation circuit of FIG. 3 is replaced with an n-type MOS transistor or a p-type MOS transistor, and the voltage generation circuit has a CMOS circuit configuration.

FIG. 7 is a schematic circuit diagram of a charge pump circuit according to the sixth embodiment of the present invention. The same reference numerals in FIGS. 2 and 3 as those in FIGS. 2 and 3 indicate components having the same functions. As can be seen by comparing these, the charge pump circuits shown in FIGS. 3 and 7 have the same configuration except for the following points.

That is, in the voltage generation circuit 26 shown in FIG. 7, the constant current circuit 26b shown in FIG. 3 is replaced with an n-type MOS transistor 26c, thereby forming a CMOS circuit. That is, the source-drain terminal of the p-type MOS transistor 26a and the drain-source terminal of the n-type MOS transistor 26c are connected in series between the power supply line and the ground line, and the drain and gate of each transistor are connected to the output line N26. It is connected.
In the voltage generation circuit 28 of FIG. 7, the constant current circuit 28b of FIG. 3 is replaced by a p-type MOS transistor 28c, thereby forming a CMOS circuit. That is, a p-type M
The source-drain terminal of the OS transistor 28c and the drain-source terminal of the n-type MOS transistor 28a are connected in series, and the drain and gate of each transistor are connected to the output line N28.

In such a CMOS circuit, the output voltage is determined according to the characteristics of the drain current with respect to the gate-source voltage of the n-type MOS transistor and the p-type MOS transistor. Since these characteristics can be adjusted by, for example, the ratio between the length and width of the channel, the output voltage can be set to a predetermined voltage.

Therefore, the same operation as the circuit shown in FIG. 3 can be realized by the charge pump circuit shown in FIG.
The overshoot current component can be effectively reduced.

<Seventh Embodiment> Next, a seventh embodiment of the present invention will be described. In the seventh embodiment, a dummy circuit for driving a dummy transistor in a phase opposite to that of a main transistor is added to an output line of a voltage generation circuit in order to suppress a voltage fluctuation of an output line of the voltage generation circuit. Has features.

FIG. 8 is a schematic circuit diagram of a charge pump circuit according to the seventh embodiment of the present invention. The same reference numerals in FIG. 8 as those in FIGS. 2 and 3 denote constituent elements having the same functions. As can be seen by comparing these, the charge pump circuit shown in FIG. 8 is provided with a dummy circuit 29 and a dummy circuit 34 in addition to the configuration of FIG.

Dummy circuit 29 has p-type MOS transistor 29a and p-type MOS transistor 29d both having a drain and a source connected to a power supply line, and a switch circuit for switching the voltage applied to the gates of these transistors. . This switch circuit has n
MOS transistor 29b, n-type MOS transistor 29e, CMOS switch 29c, and CMOS switch 29f. The CMOS switch 29c has one terminal connected to the output line N26 of the voltage generation circuit 26 and the other terminal connected to the gate of the p-type MOS transistor 29a. The CMOS switch 29f has one terminal connected to the output line N26 of the voltage generation circuit 26, and the other terminal connected to the n-type M
Connected to the gate of OS transistor 29d. n-type M
The OS transistor 29b has a source connected to the ground line and a drain connected to the gate of the p-type MOS transistor 29a. The n-type MOS transistor 29e has a source connected to the ground line and a drain connected to the gate of the p-type MOS transistor 29d. Also, n-type M
OS transistor 29e, n of CMOS switch 29c
MOS transistor and CMOS switch 29f
The signal UP is input to the gate of the p-type MOS transistor. n-type MOS transistor 29b, p-type MOS transistor of CMOS switch 29c, and CMOS
The signal / UP is input to the gate of the n-type MOS transistor of the switch 29f.

In the dummy circuit 29 having such a configuration, when the signal UP is at a high level, the gate of the p-type MOS transistor 29a is connected to the output line N26 of the voltage generation circuit 26, and the gate of the p-type MOS transistor 29d is Is connected to the ground line. When the signal UP is at a low level, the gate of the p-type MOS transistor 29a is connected to the ground line, and the gate of the p-type MOS transistor 29d is connected to the output line N2 of the voltage generation circuit 26.
6 is connected.

Therefore, when the signal UP changes from low level to high level and the gate voltage of the p-type MOS transistor 22b decreases from the power supply voltage VDD to the output voltage of the voltage generating circuit 26, p Type M
The gate voltage of the OS transistor 29a rises from the ground potential to the output voltage of the voltage generation circuit 26. When the signal UP changes from the high level to the low level and the gate voltage of the p-type MOS transistor 22a decreases from the power supply voltage VDD to the output voltage of the voltage generation circuit 26, the p-type MOS transistor 29d operates at the same timing. The gate voltage rises from the ground potential to the output voltage of the voltage generation circuit 26. Therefore, the current for charging the gate-source capacitance of p-type MOS transistor 22a and p-type MOS transistor 22b is offset by the current for charging the gate-source capacitance of p-type MOS transistor 29a and p-type MOS transistor 29d, respectively. You. That is,
Since the transient current in the output line N26 is offset and reduced, the voltage of the output line N26 can be stabilized.

Dummy circuit 34 has n-type MOS transistor 34a and n-type MOS transistor 34d both having a drain and a source connected to the ground line, and a switch circuit for switching the voltage applied to the gates of these transistors. . This switch circuit has p
MOS transistor 34b, p-type MOS transistor 34e, CMOS switch 34c, and CMOS switch 34f. The CMOS switch 34c has one terminal connected to the output line N28 of the voltage generation circuit 28 and the other terminal connected to the gate of the n-type MOS transistor 34a. The CMOS switch 34f has one terminal connected to the output line N28 of the voltage generation circuit 28, and the other terminal connected to the n-type M
Connected to the gate of OS transistor 34d. p-type M
The OS transistor 34b has a source connected to the power supply line and a drain connected to the gate of the n-type MOS transistor 34a. The p-type MOS transistor 34e has a source connected to the power supply line and a drain connected to the gate of the n-type MOS transistor 34d. In addition, p-type M
OS transistor 34b, n of CMOS switch 34c
MOS transistor and CMOS switch 34f
In the p-type MOS transistor, the signal DN is input to the gate. p-type MOS transistor 34e, p-type MOS transistor of CMOS switch 34c, and CMOS
The signal / DN is input to the gate of the n-type MOS transistor of the switch 34f.

In the dummy circuit 34 having such a configuration, when the signal DN is at a high level, the gate of the n-type MOS transistor 34a is connected to the output line N28 of the voltage generation circuit 28, and the gate of the n-type MOS transistor 34d Are connected to the power supply line. When the signal DN is at a low level, the gate of the n-type MOS transistor 34a is connected to the power supply line, and the gate of the n-type MOS transistor 34d is connected to the output line N2 of the voltage generation circuit 28.
8 is connected.

Therefore, when the signal DN changes from low level to high level and the gate voltage of the n-type MOS transistor 24a rises from the ground voltage to the output voltage of the voltage generation circuit 28, the n-type MOS transistor The gate voltage at 34a decreases from the power supply voltage VDD to the output voltage of the voltage generation circuit 28. When the signal DN changes from the high level to the low level and the gate voltage of the n-type MOS transistor 24b rises from the ground voltage to the output voltage of the voltage generation circuit 28, the gate voltage of the n-type MOS transistor 34d is changed at the same timing. The voltage drops from the power supply voltage VDD to the output voltage of the voltage generation circuit 28. Therefore, the current for charging the gate-source capacitance of n-type MOS transistor 24a and n-type MOS transistor 24b is offset by the current for charging the gate-source capacitance of n-type MOS transistor 34a and n-type MOS transistor 34d, respectively. You. That is, since the transient current in the output line N28 is canceled out and reduced, the voltage of the output line N28 can be stabilized.

As described above, also in the present embodiment, the same operation as the charge pump circuit of FIG. 3 can be realized, the overshoot current component can be effectively reduced, and the voltage generation circuit 26 and the voltage generation circuit 28 Output voltage can be stabilized. Thereby, the p-type MOS transistor 22a, the p-type MOS transistor 22b, the n-type MOS transistor
Transistor 24a and n-type MOS transistor 24
It is possible to prevent the malfunction of switching in b.

<Example of Overshoot Current Waveform>
4 shows waveform examples of an overshoot current superimposed on an input / output current of a conventional charge pump circuit and a charge pump circuit of the present invention. FIG. 9 is a diagram showing an example of input / output current waveforms of the conventional charge pump circuit shown in FIG. FIG. 10 is an enlarged view of the input / output current waveform of the charge pump circuit shown in FIG. Note that in FIGS. 9 and 10,
The horizontal axis indicates time, and the vertical axis indicates input / output current. FIG.
As can be seen from FIG. 10 and FIG. 10, in the conventional charge pump circuit, a large overshoot current is generated particularly at an initial stage when the input / output current of the charge pump circuit starts to flow. In this case, the output current from the charge pump circuit to the low-pass filter is larger than the input current.

FIG. 11 is a diagram showing an example of input / output current waveforms of the charge pump circuit of FIG. 2 according to the present invention. As can be seen by comparing FIG. 11 with FIGS. 9 and 10, the charge pump circuit according to the present invention has a significantly smaller overshoot current at the beginning and end of the flow of the input / output current than the conventional circuit.

The present invention is not limited to the above embodiment. The block diagrams and circuit diagrams of FIGS. 1 to 8 are merely examples for describing the present invention, and the present invention can be realized by various other circuits apparent to those skilled in the art. For example,
The transistor used in the present invention is not limited to a MOS transistor, and the present invention can be realized by using another transistor, for example, a bipolar transistor. Further, for example, the circuits operating as switches in the switch circuits 25 and 27 are not limited to the above-described embodiments, and some or all of them may be replaced with circuits having other switch functions.

[0091]

According to the charge pump circuit of the present invention,
The overshoot current component superimposed on the input / output current can be effectively reduced. Further, according to the phase locked loop circuit of the present invention, the overshoot current component superimposed on the input / output current of the charge pump circuit can be effectively reduced, and the phase offset can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a PLL circuit according to the present invention.

FIG. 2 is a schematic circuit diagram of a charge pump circuit according to the first embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a charge pump circuit according to a second embodiment of the present invention.

FIG. 4 is a schematic circuit diagram of a charge pump circuit according to a third embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a charge pump circuit according to a fourth embodiment of the present invention.

FIG. 6 is a schematic circuit diagram of a charge pump circuit according to a fifth embodiment of the present invention.

FIG. 7 is a schematic circuit diagram of a charge pump circuit according to a sixth embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of a charge pump circuit according to a seventh embodiment of the present invention.

FIG. 9 is a diagram showing an example of an input / output current waveform of a conventional charge pump circuit.

10 is an enlarged view of an input / output current waveform of the charge pump circuit shown in FIG.

FIG. 11 is a diagram showing an example of input / output current waveforms of the charge pump circuit according to the present invention.

FIG. 12 is a circuit diagram showing an example of a conventional charge pump circuit.

[Explanation of symbols]

10: phase frequency comparator, 20: charge pump circuit,
30 ... low-pass filter, 40 ... voltage controlled oscillator, 50
... Frequency dividers 21, 21c, 23, 23c, 26b, 28
b: constant current circuit, 21a, 21b, 22a, 22b, 2
5a, 25c, 26a, 28c, 29b, 29e, 3
4a, 34d... N-type MOS transistors, 23a, 23
b, 24a, 24b, 26c, 27a, 27c, 28
a, 29a, 29d, 34b, 34e ... p-type MOS transistors, 25b, 25d, 27b, 27d, 29c,
29f, 34c, 34f... CMOS switch, C26,
C28 ... Capacitor

Claims (17)

[Claims] A current input / output terminal; a first constant current circuit for controlling a current flowing from a first potential to an output terminal to a constant value;
A first transistor for controlling a conduction current flowing from the output terminal of the constant current circuit to the current input / output terminal; and a first transistor for controlling a level of a signal input to the control terminal.
A second transistor that controls a conduction current flowing from an output terminal of the constant current circuit to a second potential lower than the first potential, and a first transistor that responds to a first control signal that is input. The signal of the first level which is brought into the conductive state is transmitted to the first level.
And a second level signal that causes the second transistor to become non-conductive is input to the control terminal of the second transistor.
And a second state in which the signal of the second level is input to the control terminal of the first transistor and the signal of the first level is input to the control terminal of the second transistor. A first conduction control circuit for switching, a second constant current circuit for controlling the current flowing from the input terminal to the second potential to be constant, A third transistor for controlling a conduction current flowing from a terminal to an input terminal of the second constant current circuit; and a first transistor for controlling a level of a signal input to a control terminal.
A fourth transistor that controls a conduction current flowing from the potential of the second constant current circuit to the input terminal of the second constant current circuit; and a third transistor that conducts the third transistor in response to the input second control signal. Signal of the third level
And a third level signal for inputting a fourth level signal at which the fourth transistor is turned off to the control terminal of the fourth transistor.
And a fourth state in which the signal of the fourth level is input to the control terminal of the third transistor and the signal of the third level is input to the control terminal of the fourth transistor. And a second conduction control circuit for switching. 2. The first transistor and the second transistor
When the voltage level of the control terminal is the same, the conduction currents are close to each other. When the voltage level of the control terminal is the same, the third transistor and the fourth transistor The charge pump circuit according to claim 1, wherein the conduction currents are close to each other. 3. The first transistor and the second transistor.
3. The transistor according to claim 2, wherein the third transistor and the fourth transistor are transistors having an equivalent structure having a form similar to each other. Charge pump circuit. 4. The first conduction control circuit switches between the input first-level signal and the input second-level signal in response to the first control signal. The control terminal of the first transistor and the second terminal
A first switch circuit that outputs a signal to the control terminal of each of the transistors. The second conduction control circuit receives the third level signal or the third level signal in response to the second control signal. The charge pump circuit according to claim 1, further comprising a second switch circuit that switches the signal of the fourth level and outputs the signal to the control terminal of the third transistor and the control terminal of the fourth transistor. 5. The first switch circuit, wherein the second level signal is inputted to a source, a drain is connected to a control terminal of the first transistor, and the first switch circuit is turned off in the first state. The p-type field-effect transistor that is conductive in the second state is connected to the drain and source of each other, the first level signal is input to one of the connections, and the other of the connection is A first parallel connection of an n-type field-effect transistor and a p-type field-effect transistor, which is connected to a control terminal of a first transistor, becomes conductive in the first state, and becomes non-conductive in the second state; A second level signal is input to a circuit and a source; a drain is connected to a control terminal of the second transistor; the circuit is in a conductive state in the first state; and a non-conductive state in the second state The drain and the source of each other are connected to each other, the signal of the first level is input to one of the connections, and the other of the connections is connected to the control terminal of the second transistor. And a second parallel circuit of an n-type field-effect transistor and a p-type field-effect transistor, which is turned off in the first state and turned on in the second state, In the switch circuit, the signal of the fourth level is input to the source, the drain is connected to the control terminal of the third transistor, the switch is turned off in the third state, and turned on in the fourth state. The drain and the source are connected to each other, the third level signal is input to one of the connections, and the other of the connection is connected to the third transistor of the third transistor. A third parallel circuit of an n-type field effect transistor and a p-type field effect transistor, which is connected to a control terminal, becomes conductive in the third state, and becomes non-conductive in the fourth state; An n-type field effect in which the signal of the fourth level is input, the drain is connected to the control terminal of the fourth transistor, the third state is turned on, and the fourth state is turned off. The transistor, the drain and the source thereof are connected to each other, the third level signal is input to one of the connections, the other of the connections is connected to the control terminal of the fourth transistor, and the third 5. The charge pump according to claim 4, further comprising: a fourth parallel circuit of an n-type field effect transistor and a p-type field effect transistor that is turned off in the state and turned on in the fourth state. 6. Circuit. 6. The at least one of the first parallel circuit, the second parallel circuit, the third parallel circuit, and the fourth parallel circuit has one of transistors connected in parallel deleted. The charge pump circuit according to claim 5, having a configuration. 7. The first switch circuit, wherein the second level signal is input to a source, a drain is connected to a control terminal of the first transistor, and the first switch circuit is turned off in the first state. A p-type field-effect transistor that becomes conductive in the second state, a source of the first-level signal, a drain connected to a control terminal of the first transistor, and a first state of the first state. A p-type field-effect transistor that is turned on in the second state and is turned off in the second state; a signal of the second level is input to a source; a drain is connected to a control terminal of the second transistor; A p-type field-effect transistor that becomes conductive in the first state and becomes non-conductive in the second state; a signal of the first level is input to a source; A p-type field effect transistor that is connected to a control terminal of the transistor, becomes non-conductive in the first state, and becomes conductive in the second state; And an n-type field effect transistor that receives a signal of level 4 and has a drain connected to the control terminal of the third transistor, becomes non-conductive in the third state, and becomes conductive in the fourth state. The source is supplied with the signal of the third level, the drain is connected to the control terminal of the third transistor, the conductive state is established in the third state, and the non-conductive state is established in the fourth state. A source of the fourth level signal, a drain connected to a control terminal of the fourth transistor, and a conductive state in the third state; An n-type field-effect transistor that is turned off in the fourth state; a signal of the third level is input to a source; a drain is connected to a control terminal of the fourth transistor; 5. The charge pump circuit according to claim 4, further comprising: a p-type field-effect transistor that is turned off in the fourth state and is turned on in the fourth state. 8. The first switch circuit, wherein the signal of the second level is input to a source, a drain is connected to a control terminal of the first transistor, and the first switch circuit is turned off in the first state. A p-type field-effect transistor that becomes conductive in the second state; a signal of the first level input to a drain; a source connected to a control terminal of the first transistor; An n-type field-effect transistor which becomes conductive in the second state and becomes non-conductive in the second state, a signal of the second level is input to a source, and a drain is connected to a control terminal of the second transistor; A p-type field-effect transistor that becomes conductive in the first state and becomes non-conductive in the second state; a signal of the first level is input to a drain; An n-type field effect transistor connected to a control terminal of the transistor, being non-conductive in the first state, and being conductive in the second state, wherein the second switch circuit has the source And an n-type field effect transistor that receives a signal of level 4 and has a drain connected to the control terminal of the third transistor, becomes non-conductive in the third state, and becomes conductive in the fourth state. The third-level signal is input to the drain, the source is connected to the control terminal of the third transistor, the third state becomes conductive, and the fourth state becomes non-conductive. A source of the fourth level signal, a drain connected to a control terminal of the fourth transistor, and a conductive state in the third state; An n-type field effect transistor that is turned off in the fourth state; a signal of the third level is input to a drain; a source is connected to a control terminal of the fourth transistor; 5. The charge pump circuit according to claim 4, further comprising: an n-type field-effect transistor that is turned off in the first state and is turned on in the fourth state. 9. The first conduction control circuit includes: a first voltage generation circuit that generates the first level voltage; and a filter circuit that attenuates a noise component in an output line of the first voltage generation circuit. The second conduction control circuit includes: a second voltage generation circuit that generates the second level voltage; a filter circuit that attenuates a noise component in an output line of the second voltage generation circuit; The charge pump circuit according to claim 4, comprising: 10. The first conduction control circuit according to claim 1, wherein the first potential control circuit includes: a first level voltage output terminal; and a control terminal connected to the first level. And a constant current circuit for controlling a current flowing from the output terminal to the second potential to a constant current, wherein the second conduction control circuit includes a transistor for controlling the third level. A voltage output terminal; a transistor that controls a current flowing from the output terminal to the second potential according to a voltage level of a control terminal connected to the output terminal; and a transistor that flows from the first potential to the output terminal. The charge pump circuit according to claim 4, further comprising: a constant current circuit that controls a current to a constant current. 11. The first conduction control circuit according to claim 1, wherein:
And a capacitor connected between the voltage output terminal at the first level and the first potential or the second potential. The second conduction control circuit includes a voltage output terminal at the third level and the second level. The charge pump circuit according to claim 10, further comprising a capacitor connected between the first potential and the second potential. 12. The first conduction control circuit, comprising: a first-level voltage output terminal; a p-type electric field having a drain and a gate connected to the output terminal, and a source connected to the first potential. An effect transistor, an n-type field effect transistor having a drain and a gate connected to the output terminal, and a source connected to the second potential, wherein the second conduction control circuit comprises: A voltage output terminal, an n-type field effect transistor having a drain and a gate connected to the output terminal, and a source connected to the second potential; a drain and a gate connected to the output terminal; The charge pump circuit according to claim 4, further comprising: a p-type field-effect transistor connected to the potential of the charge pump. 13. The first conduction control circuit according to claim 1, wherein
And a capacitor connected between the voltage output terminal at the first level and the first potential or the second potential. The second conduction control circuit includes a voltage output terminal at the third level and the second The charge pump circuit according to claim 12, further comprising a capacitor connected between the first potential and the second potential. 14. The first conduction control circuit, further comprising: a fifth transistor and a sixth transistor having an input / output terminal connected to the first potential; and the first level in the first state. Is input to the control terminal of the fifth transistor, the control terminal of the sixth transistor is connected to the second potential, and in the second state, the signal of the first level is transmitted to the control terminal of the fifth transistor. 6 is connected to the control terminal of the sixth transistor, and the control terminal of the fifth transistor is connected to the second potential.
Wherein the second conduction control circuit comprises: a seventh transistor and an eighth transistor having input / output terminals connected to the second potential; and the third transistor in the third state. Is input to the control terminal of the seventh transistor, the control terminal of the eighth transistor is connected to the first potential, and in the fourth state, the signal of the third level is A fourth terminal that inputs the control terminal of the eighth transistor and connects the control terminal of the seventh transistor to the first potential.
The charge pump circuit according to claim 4, comprising: 15. A phase comparison circuit for comparing a phase difference between an input signal and a feedback signal and outputting a first control signal and a second control signal having a level corresponding to the comparison result, A charge pump circuit that inputs or outputs a current according to the level of a control signal and the second control signal, a smoothing circuit that receives an input / output current of the charge pump circuit and outputs a smoothed voltage, A phase-locked loop circuit having a voltage-controlled oscillation circuit for generating the feedback signal having a frequency corresponding to the output voltage of the smoothing circuit, wherein the charge pump circuit comprises: a current input / output terminal; A first constant current circuit for controlling the current flowing to the control terminal at a constant level;
A first transistor for controlling a conduction current flowing from the output terminal of the constant current circuit to the current input / output terminal; and a first transistor for controlling a level of a signal input to the control terminal.
A second transistor for controlling a conduction current flowing from an output terminal of the constant current circuit to a second potential lower than the first potential, and the first transistor being in a conductive state in response to the first control signal Is input to the control terminal of the first transistor, and a second level signal at which the second transistor is turned off is input to the control terminal of the second transistor. A first state, or a second state, in which the signal of the second level is input to the control terminal of the first transistor and the signal of the first level is input to the control terminal of the second transistor. A first conduction control circuit for switching the state of the second terminal, a second constant current circuit for controlling the current flowing from the input terminal to the second potential to a constant value, and a control circuit according to the level of the signal input to the control terminal. A third transistor for controlling the conduction current flowing from the current input and output terminals to the input terminal of the second constant current circuit, according to the level of the signal input to the control terminal, the first
A fourth transistor for controlling a conduction current flowing from the potential of the second constant current circuit to an input terminal of the second constant current circuit; and a third level at which the third transistor is turned on in response to the second control signal. A third state in which the signal of the fourth level is input to the control terminal of the third transistor, and a signal of a fourth level at which the fourth transistor is turned off is input to the control terminal of the fourth transistor; Alternatively, a second state in which the fourth level signal is input to the control terminal of the third transistor and the fourth state in which the third level signal is input to the control terminal of the fourth transistor is switched. And a continuity control circuit. 16. The first transistor and the second transistor, when the voltage level of the control terminal is the same, the conduction currents are close to each other, and the third transistor and the fourth transistor are 16. The phase locked loop circuit according to claim 15, wherein the conduction currents are close to each other when the voltage levels of the control terminals are the same. 17. The first transistor and the second transistor are transistors having an equivalent structure having a form similar to each other, and the third transistor and the fourth transistor are forms having a form similar to each other. 17. The phase-locked loop circuit according to claim 16, wherein the phase-locked loop circuit is a transistor having an equivalent structure.