JP2012009993A - Charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump circuit speeding up rise of a charging/discharging current, and having no possibility of a malfunction.SOLUTION: A first current mirror circuit is composed of a transistor Mp1 diode-connected, a transistor Mp2, and a transistor Mp3 controlled by a command signal UPb to connect gates of the Mp1 and the Mp2. A transistor Mp4 controlled by the command signal UPb is connected between a gate electrode of the transistor Mp2 and a power supply VDD. A second current mirror circuit is composed of a transistor Mn1 diode-connected, a transistor Mn2, and a transistor Mn3 controlled by a command signal DN to connect gates of the Mn1 and the Mn2. Between a gate electrode of the Mn2 and a ground, a transistor Mn4 controlled by a command signal DNb is connected.

Description

  The present invention relates to a charge pump circuit used in a PLL (Phase Locked Loop) circuit, and more particularly, to a small charge pump circuit formed of an integrated circuit.

FIG. 4 is a block diagram showing a general configuration of a charge pump type PLL circuit.
The PLL circuit 1 includes a phase comparator 2, a charge pump circuit 3, a loop filter 4, and a voltage controlled oscillator 5. A VCO signal that is an output of the voltage controlled oscillator 5 is fed back to the phase comparator 2 together with a reference clock. ing. The phase comparator 2 compares the phase of the reference clock and the phase of the VCO signal of the voltage controlled oscillator 5 (the divided signal thereof). If the phase of the VCO signal is delayed compared to the reference clock, the charge pump circuit 3 A command signal UP for increasing the frequency is output. When the phase of the VCO signal is advanced compared to the reference clock, a command signal DN for lowering the frequency is output. In the charge pump circuit 3, when the command signal UP is input, a charge current is supplied to the loop filter 4 to increase the oscillation frequency in the voltage control oscillator 5 in the subsequent stage. When the command signal DN is input, The electric charge of the loop filter 4 is discharged, and the oscillation frequency in the voltage control oscillator 5 in the subsequent stage is decreased.

  The voltage controlled oscillator 5 is supplied with the analog signal output from the loop filter 4 and outputs a VCO signal having a frequency corresponding to the analog signal. When the VCO signal of the voltage controlled oscillator 5 is fed back, it is divided into 1 / N (N: an arbitrary natural number) by using a frequency divider composed of a counter and then supplied to the phase comparator 2. For example, the VCO signal can be N times the frequency of the reference clock. Therefore, by arbitrarily setting the value of N, it is possible to obtain a frequency that is an arbitrary natural number multiple of the frequency with respect to the input reference clock.

FIG. 5 is a circuit diagram showing a configuration of a conventional charge pump circuit.
In the charge pump circuit 3, a constant current circuit 31 and a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) Mp0 are connected in series between the power supply VDD and the output terminal OUT. The constant current circuit 31 includes first and second P-channel MOSFETs Mp1 and Mp2 that are mirror-connected and a current source 32. Of these, the drain electrode of the second P-channel MOSFET Mp2 is the source electrode of the P-channel MOSFET Mp0. It is connected. A signal UPb obtained by inverting the command signal UP is supplied to the gate electrode of the P-channel MOSFET Mp0 and operates as an analog switch. In the constant current circuit 31, the gate electrodes of the first and second P-channel MOSFETs Mp1 and Mp2 are connected to each other to form a first current mirror circuit, and the drain electrode of the first P-channel MOSFET Mp1 Each gate electrode is connected to a current source 32. In the second P-channel MOSFET Mp2, the parasitic capacitance Cpp between the drain electrode and the substrate electrode is indicated by a broken line.

  On the other hand, a constant current circuit 33 and an N channel MOSFET (hereinafter referred to as N channel MOSFET) Mn0 are connected in series to the ground side of the charge pump circuit 3. The constant current circuit 33 includes first and second N-channel MOSFETs Mn1 and Mn2 that are mirror-connected and a current source 34. Of these, the drain electrode of the second N-channel MOSFET Mn2 is connected to the source electrode of the N-channel MOSFET Mn0. It is connected. The N-channel MOSFET Mn0 is supplied with a command signal DN at its gate electrode and operates as an analog switch. In the constant current circuit 33, the gate electrodes of the first and second N-channel MOSFETs Mn1 and Mn2 are connected to each other to form a second current mirror circuit, and the drain electrode of the first N-channel MOSFET Mn1 and Each gate electrode is connected to a current source 34.

  In the second N-channel MOSFET Mn2, the parasitic capacitance Cpn between the drain electrode and the substrate electrode is indicated by a broken line. The drain electrode of the N-channel MOSFET Mn0 is connected to the output terminal OUT together with the drain electrode of the P-channel MOSFET Mp0, and controls the charge / discharge current to the loop filter 4 at the subsequent stage.

  When the command signal UP becomes H (High) level, the inverted L (Low) level signal UPb is supplied to the gate electrode of the P-channel MOSFET Mp0 and becomes conductive, so that the constant current circuit 31 supplies the output terminal OUT. Charging current flows. On the contrary, when the command signal DN becomes H level, the N-channel MOSFET Mn0 of the charge pump circuit 3 becomes conductive, and a discharge current flows from the output terminal to the constant current circuit 33.

  In such a current mirror circuit composed of P-channel MOSFETs Mp1, Mp2 and N-channel MOSFETs Mn1, Mn2, a relatively large transistor is used. Therefore, parasitic capacitances Cpp and Cpn mainly including the above-described junction capacitance (floating capacitance) are generated between the drain electrodes of the P-channel MOSFET Mp2 and the N-channel MOSFET Mn2 and the substrate, and these parasitic capacitances are analog. This affects the operation of the charge pump circuit 3 as a circuit.

  That is, when the P-channel MOSFET Mp0 is not conducting, the drain potential of the P-channel MOSFET Mp2 is equal to the potential Vdd of the power supply VDD, and when the P-channel MOSFET Mp0 is conducting, the drain potential of the P-channel MOSFET Mp2 is equal to the potential Vout ( However, Vdd> Vout> 0). Therefore, when the P-channel MOSFET Mp0 is conductive, the charge Qu having the magnitude of Cpp (Vdd−Vout) flows out to the output terminal via the parasitic capacitance Cpp. Similarly, when the N-channel MOSFET Mn0 is turned on, a charge Qd having a magnitude of Cpn × Vout flows from the output terminal to the parasitic capacitance Cpn.

  Therefore, when the pulse width of the command signal UP or DN immediately before the PLL circuit 1 is locked is in a narrow state, the parasitic capacitance Cpp when the P-channel MOSFET Mp0 and the N-channel MOSFET Mn0 are turned on compared to the original charge / discharge current. And the magnitude of the electric charge flowing to the output terminal OUT via Cpn cannot be ignored. As a result, the PLL circuit 1 has an inconvenience that its operation becomes unstable or locks with a large phase difference.

  This type of problem becomes conspicuous when the magnitude of the charge / discharge current is reduced from the viewpoint of reducing power consumption in the PLL circuit 1 or reducing the area of the loop filter. A charge pump circuit that eliminates the influence of such parasitic capacitance is disclosed in Patent Document 1 described below as a technique for canceling the charge accumulated in the parasitic capacitance.

  Patent Document 1 provides two methods or two charge pump circuits for setting the drain potential of the transistors Mp2 and Mn2 to the same potential as the output terminal potential Vout by using an amplifier and a switch when the transistors Mp0 and Mn0 are shut off. A method for canceling the influence of the inflowing charge due to the parasitic capacitance is described. However, when the PLL circuit is configured as an integrated circuit, there remains a problem that the circuit configuration becomes complicated.

In Patent Document 2, a source current (Isource) is supplied from a charge pump circuit (CPC) to a low-pass filter (LFC in FIG. 6 of the same document), or a sink current (Isink) from a low-pass filter (LFC). The invention of a fractional synthesizer that generates a phase control voltage for controlling the oscillation frequency (f _RFVCO ) of the voltage controlled oscillator RFVCO is described.

FIG. 6 is a circuit diagram showing a configuration of a conventional charge pump circuit disclosed in Patent Document 2. In FIG.
Here, the switch (up switch 10) in which the gate input terminal of the P channel MOS transistor (MP1) of the charge pump circuit (CPC) is driven by the output signal Q (VQREF) of the up flip flop (FF_Up). The gate input terminal of the N-channel MOS transistor (MN1) is controlled by a switch (down switch 20) driven by the output signal Q (VQDIV) of the down flip-flop (FF_Dn). In this case, when the supply of the source current (Isource) is stopped, the potential of the gate input terminal of the P-channel MOS transistor (MP1) is set to the H level by the up switch 10 driven by the signal VQREF. MP1) has a high impedance between the source and drain. When stopping the supply of the sink current (I sink), the potential of the gate input terminal of the N channel MOS transistor (MN1) is set to L level by the down switch 20 driven by the output signal VQDIV. The impedance between the source and drain of MN1) is set high. By applying the technique of Patent Document 2 to the conventional charge pump circuit shown in FIG. 5, the parasitic capacitance Cpn of the N-channel MOSFET Mn2 and the parasitic capacitance Cpp of the P-channel MOSFET Mp2 are directly connected to the output terminal OUT, and the P-channel MOS The drain voltages of the transistor Mp2 and the N-channel MOS transistor Mn2 are always the potential Vout of the output terminal OUT. Therefore, it is possible to easily eliminate the influence of the parasitic capacitance in the charge pump circuit (CPC) generated in the configuration shown in FIG.

Japanese Patent Laid-Open No. 9-266443 (see paragraph numbers [0039] to [0070], FIGS. 1 to 7) JP 2007-318290 A (see paragraph numbers [0024] and [0025] and FIG. 6)

  However, in the charge pump circuit (CPC) described in Patent Document 2, the up switch 10 and the down switch 20 are alternately short-circuited to stop the supply of the source current (Isource) and the sink current (I sink). In order to supply the source current (Isource) to the low-pass filter (LFC) when the supply of the source current (Isource) or the sink current (Isink) is started when these switches are opened (off) from the state of It is necessary to charge the gate capacities of the two N-channel MOS transistors (MN1, MN0) in order to charge the gate capacities of the two P-channel MOS transistors (MP1, MP0) or to allow the sink current (Isink) to flow. Since such a charging time is required, current supply to the subsequent low-pass filter (LFC) is actually started or discharged with respect to the timing of the output signal (Q) from the preceding phase comparator (PDC). There has been a problem that a delay occurs in the timing at which is started.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a charge pump circuit that speeds up the charging / discharging current and does not cause a malfunction.

According to the present invention, there is provided a charge pump circuit that supplies a current to a loop filter connected to a subsequent stage in response to a command signal of a phase comparator connected to the previous stage.
In the charge pump circuit, a gate is driven by a first P-channel MOSFET, a second P-channel MOSFET, and a first signal that are diode-connected and supplied with a constant current, and the first P-channel MOSFET and the first P-channel MOSFET A first current mirror circuit composed of a third P-channel MOSFET for connecting the gates of the two P-channel MOSFETs, and a gate driven by a signal obtained by inverting the first signal, and the second P-channel MOSFET A fourth P-channel MOSFET for connecting between the gate of the first power source and the first power supply, a first N-channel MOSFET connected to a diode and supplied with a constant current, a second N-channel MOSFET, and a gate with a second signal Between the gates of the first N-channel MOSFET and the second N-channel MOSFET. A gate is driven by a second current mirror circuit composed of a third N-channel MOSFET to be connected, and a signal obtained by inverting the second signal, and between the gate of the second N-channel MOSFET and a second power source. A fourth P-channel MOSFET to be connected, and each drain of the second P-channel MOSFET and the second N-channel MOSFET is connected to serve as an output terminal.

  In the charge pump circuit of the present invention, the risk of malfunction can be eliminated by controlling the output current with a simple circuit configuration and suppressing glitch noise.

1 is a circuit diagram showing a charge pump circuit according to a first embodiment. FIG. It is a circuit diagram which shows the charge pump circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the charge pump circuit which concerns on 3rd Embodiment. It is a block diagram which shows the general structure of a charge pump type PLL circuit. It is a circuit diagram which shows the structure of the conventional charge pump circuit. It is a circuit diagram which shows the structure of the conventional charge pump circuit currently disclosed by patent document 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a charge pump circuit according to the first embodiment.
Here, the first current is generated by the diode-connected first P-channel MOSFET Mp1, the second P-channel MOSFET Mp2, and the third P-channel MOSFET Mp3 connecting the gates of the first and second P-channel MOSFETs Mp1 and Mp2. A mirror circuit is configured. The command signal UPb is supplied to the gate electrode of the third P-channel MOSFET Mp3. A fourth P-channel MOSFET Mp4 is connected between the gate electrode of the second P-channel MOSFET Mp2 and the power supply VDD, and a command signal UP is supplied to the gate electrode.

  Further, the second current mirror is provided by the diode-connected first N-channel MOSFET Mn1, second N-channel MOSFET Mn2, and third N-channel MOSFET Mn3 connecting the gates of the first and second N-channel MOSFETs Mn1 and Mn2. A circuit is configured. A command signal DN is supplied to the gate electrode of the third N-channel MOSFET Mn3. A fourth N-channel MOSFET Mn4 controlled by a command signal DNb is connected between the gate electrode of the second N-channel MOSFET Mn2 and the ground (ground).

  Here, the command signals UP and UPb and the command signals DN and DNb are controlled at the L level and the H level so that they are mutually inverted signals. The parts corresponding to the conventional circuit in FIG.

Next, the operation of the charge pump circuit configured as described above will be described.
Now, when the command signal UP to the first current mirror circuit becomes H level, the inverted command signal UPb becomes L level, and the P-channel MOSFET Mp3 is turned on and the P-channel MOSFET Mp4 is cut off at the same time. Therefore, the gate potential of the P-channel MOSFET Mp2 becomes equal to the gate potential of the P-channel MOSFET Mp1, and a current corresponding to the mirror ratio of the first current mirror circuit flows from the power supply VDD to the second P-channel MOSFET Mp2. Therefore, a predetermined charging current is supplied from the output terminal OUT to the loop filter 4 in the subsequent stage. Unlike the conventional circuit shown in FIG. 5, the parasitic capacitance Cpp of the second P-channel MOSFET Mp2 is directly connected to the output terminal OUT. Therefore, there is no risk of unnecessary charges flowing out from there.

  In the present embodiment, the rise of the on-current of the P-channel MOSFET Mp2 is accelerated for the following reason. That is, when charging current supply from the first current mirror circuit to the subsequent loop filter 4 is started, in Patent Document 2, the gate capacitances of the two P-channel MOSFETs Mp1 and Mp2 constituting the current mirror circuit are used as the current of the current source 32. It is necessary to charge from zero with Ibu, and therefore the rise of the on-current of the P-channel MOSFET Mp2 is delayed. On the other hand, in the present embodiment, even when the P-channel MOSFET Mp3 is cut off, the gate potential of the P-channel MOSFET Mp1 remains at a level necessary for flowing the current Ibu of the current source 32. At the moment when the P-channel MOSFET Mp3 is turned on, the charge of the gate capacitance of the P-channel MOSFET Mp1 is redistributed to the gate capacitance of the P-channel MOSFET Mp1 and the gate capacitance of the P-channel MOSFET Mp2, and supply of a certain amount of current by the P-channel MOSFET Mp2 is instantly started. The Thereafter, the two gate capacitors are charged by the current Ibu of the current source 32. This is because only the amount of charge that charges the gate capacitor of one P-channel MOSFET Mp2 needs to be supplied, and the charging time can be shortened. That is, in the case of Patent Document 2, the supply current gradually increases from zero, but in this embodiment, supply of a current at a certain level is instantaneously started, and a predetermined current value thereafter is output. The time until it can be shortened.

  On the contrary, when the command signal UP becomes L level, the inverted command signal UPb becomes H level, the P-channel MOSFET Mp4 is turned on and the P-channel MOSFET Mp3 is cut off. Therefore, the gate potential of the P-channel MOSFET Mp2 becomes equal to the potential of the power supply VDD, and no current flows through the output terminal OUT. Further, the gate potential of the P-channel MOSFET Mp1 remains at a level necessary for flowing the current Ibu to the current source 32.

  On the other hand, when the command signal DN to the second current mirror circuit becomes H level, the inverted command signal DNb becomes L level, and the N-channel MOSFET Mn3 becomes conductive and the N-channel MOSFET Mn4 is cut off at the same time. Therefore, the gate potentials of the N-channel MOSFETs Mn1 and Mn2 become equal, and a discharge current corresponding to the mirror ratio of the second current mirror circuit flows from the output terminal OUT to the second N-channel MOSFET Mn2. That is, a current is drawn from the subsequent loop filter 4 to the N-channel MOSFET Mn2, but even at that time, the parasitic capacitance Cpn of the N-channel MOSFET Mn2 is directly connected to the output terminal OUT, so there is no possibility that unnecessary charge flows there. .

  In the present embodiment, the rise of the on-current of the N-channel MOSFET Mn2 is accelerated for the following reason. That is, when the drawing of the discharge current from the subsequent loop filter 4 by the second current mirror is started, in Patent Document 2, the gate capacitances of the two N-channel MOSFETs Mn1 and Mn2 constituting the current mirror are set to the current Ibd of the current source 34. Therefore, the on-current rise of the N-channel MOSFET Mn2 is delayed. On the other hand, in the present embodiment, even when the N-channel MOSFET Mn3 is cut off, the gate potential of the N-channel MOSFET Mn1 remains at a level necessary for flowing the current Ibd of the current source 34. At the instant when the N-channel MOSFET Mn3 is turned on, the charge of the gate capacitance of the N-channel MOSFET Mn1 is redistributed to the gate capacitance of the N-channel MOSFET Mn1 and the gate capacitance of the N-channel MOSFET Mn2, and a certain amount of current drawing by the N-channel MOSFET Mn2 is instantly started. The After that, the two gate capacitors are charged by the current Ibd of the current source 34. This is because only the amount of charge that charges the gate capacitor of one N-channel MOSFET Mn2 needs to be supplied, and the charging time can be shortened. That is, in the case of Patent Document 2, the drawn current gradually increases from zero, but in this embodiment, the drawing of a certain level of current is started instantaneously, so that a predetermined current value thereafter is drawn. Can be shortened.

  On the contrary, when the command signal DN becomes L level, the inverted command signal DNb becomes H level, the N-channel MOSFET Mn4 is turned on and the N-channel MOSFET Mn3 is cut off. Therefore, the gate potential of the N-channel MOSFET Mn2 becomes equal to the ground potential, and no current flows there. Further, the gate potential of the N-channel MOSFET Mn1 remains at a level necessary for flowing the current Ibd from the current source 34.

Note that if the command signals UP and DN are both at the L level, neither of the two current mirror circuits operates.
FIG. 2 is a circuit diagram showing a charge pump circuit according to the second embodiment.

  Here, a capacitor Cu is provided between the gate electrode of the first P-channel MOSFET Mp1 in the first current mirror circuit and the power supply VDD, and similarly, the gate electrode of the first N-channel MOSFET Mn1 in the second current mirror circuit A capacitor Cd is provided between the grounds. Thereby, compared with the charge pump circuit of FIG. 1, the rise of the current of the two current mirror circuits is further accelerated.

  That is, the charge distributed to the gate capacitance of the P-channel MOSFET Mp2 or N-channel MOSFET Mn2 increases at the moment when the P-channel MOSFET Mp3 or N-channel MOSFET Mn3 becomes conductive, and immediately after the P-channel MOSFET Mp3 or N-channel MOSFET Mn3 becomes conductive, the P-channel MOSFET Mp2 or N The current flowing through the channel MOSFET Mn2 can be made larger than that in the first embodiment, that is, close to the final value. Here, as the capacitances of the capacitors Cu and Cd are increased, the current flowing through the P-channel MOSFET Mp2 or N-channel MOSFET Mn2 immediately after the P-channel MOSFET Mp3 or N-channel MOSFET Mn3 is conducted can be made closer to the final value.

Accordingly, the response characteristic of the loop filter 4 connected in the subsequent stage is improved, and a PLL circuit with few malfunctions can be realized with a circuit having a small area.
FIG. 3 is a circuit diagram showing a charge pump circuit according to the third embodiment.

  Here, the gate electrode of the first P-channel MOSFET Mp1 and the drain electrode of the third P-channel MOSFET Mp3 in the first current mirror circuit are connected by the voltage follower amplifier X1u, and similarly, the second current mirror circuit. The gate electrode of the first N-channel MOSFET Mn1 and the drain electrode of the third N-channel MOSFET Mn3 are connected by a voltage follower amplifier X1d. When the P-channel MOSFET Mp3 and the N-channel MOSFET Mn3 are turned on, these voltage follower amplifiers X1u and X1d charge the gate capacitances of the P-channel MOSFET Mp2 and the N-channel MOSFET Mn2 with a larger current driving capability than the current sources 32 and 34. Rising delays can be eliminated.

  In any of the embodiments, the current mirror circuit can be realized with a simple circuit configuration, and a charge pump circuit can be provided in which the rise time of the charge / discharge current is increased and there is no possibility of malfunction.

DESCRIPTION OF SYMBOLS 1 PLL circuit 2 Phase comparator 3 Charge pump circuit 4 Loop filter 5 Voltage controlled oscillator 31, 33 Constant current circuit 32, 34 Current source Cpp, Cpn Parasitic capacitance Mn0 to Mn4 N channel MOSFET
Mp0-Mp4 P-channel MOSFET
X1u, X1d Voltage follower amplifier

Claims (3)

In the charge pump circuit for supplying current to the loop filter connected to the subsequent stage according to the command signal of the phase comparator connected to the previous stage,
A gate is driven by a first P-channel MOSFET, a second P-channel MOSFET, and a first signal, which are diode-connected and supplied with a constant current, and the first P-channel MOSFET and the second P-channel MOSFET A first current mirror circuit comprising a third P-channel MOSFET connecting the gates;
A fourth P-channel MOSFET for driving a gate with a signal obtained by inverting the first signal and connecting between the gate of the second P-channel MOSFET and a first power supply;
A gate is driven by a first N-channel MOSFET, a second N-channel MOSFET, and a second signal that are diode-connected and supplied with a constant current, and the first N-channel MOSFET and the second N-channel MOSFET A second current mirror circuit composed of a third N-channel MOSFET connecting the gates;
A fourth P-channel MOSFET for driving a gate with a signal obtained by inverting the second signal and connecting between the gate of the second N-channel MOSFET and a second power supply;
The charge pump circuit is characterized in that each drain of the second P-channel MOSFET and the second N-channel MOSFET is connected to be an output terminal. In the first current mirror circuit, a first capacitor is provided between the gate of the first P-channel MOSFET and the first power supply,
2. The charge pump circuit according to claim 1, wherein the second current mirror circuit is provided with a second capacitor between a gate of the first N-channel MOSFET and the second power supply. . In the first current mirror circuit, a first voltage follower circuit is provided between the gate of the first P-channel MOSFET and the third P-channel MOSFET,
2. A second voltage follower circuit is provided between the gate of the first N-channel MOSFET and the third N-channel MOSFET in the second current mirror circuit. Charge pump circuit.

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