JP2008042339A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a PLL circuit which is suitable for a fine process and whose performance is improved. <P>SOLUTION: Reference signals and feedback signals are compared with each other in a phase comparator. A charge pump circuit is controlled by the phase comparison output of the phase comparator, and the output current is supplied to a filter & voltage/current conversion circuit to control an oscillation circuit. The output signals of the oscillation circuit are frequency-divided in a frequency divider circuit, the feedback signals are formed and the PLL circuit is constituted. The filter & voltage/current conversion circuit comprises: an output MOSFET where the output signals of a differential amplifier circuit to the input of which a bias voltage is supplied are supplied to a gate; a resistor element provided to the drain of the output MOSFET; and a capacitor provided between the drain of the output MOSFET and the other input of the differential amplifier circuit. The output current of the charge pump circuit is supplied to the other input of the differential amplifier circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and, for example, to a technique that is effective when applied to a PLL (phase locked loop) circuit including a VCO configured using a voltage-current conversion circuit.

A frequency phase comparator (hereinafter referred to as PFD), a charge pump circuit (hereinafter referred to as CP), a filter (hereinafter referred to as LPF), and a voltage controlled oscillator (hereinafter referred to as VCO), and a phase difference signal between an input reference clock and an oscillation output clock. The following non-patent documents 1 to 3 are examples of a PLL circuit that performs phase control by performing frequency control by smoothing with a filter and supplying it to a VCO. There are VCO configurations that directly control the frequency with voltage as in Non-Patent Document 3, and there are combinations of current-controlled oscillators (CCO or ICO) and voltage-current converter VIC as in Non-Patent Documents 1 and 2. The filter output voltage is used as the gate input of the MOSFET.
2004 Symposium on VLSI Circuits Digest of Technical Papers `` A 0.6-1.2V Low-Power Configurable PLL Architecture for 6GHz-300MHz Applications in a 90nm CMOS Process '' 2003 Symposium on VLSI Circuits Digest of Technical Papers `` A Design of a Compact 2GHz -PLL with a New Adaptive Active Loop Filter Circuit '' 2000 Symposium on VLSI Circuits Digest of Technical `` Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers ''

  FIG. 5 shows a circuit diagram of a PLL circuit studied prior to the present invention. This PLL circuit performs frequency control by forming a phase difference signal between the input reference clock and the oscillation output clock with PFD and CP, smoothing with LPF, and supplying to the VCO as in Non-Patent Documents 1 and 2 above. Lock the phase. The configuration of the VCO is that the control voltage VC formed by the LPF is converted into a current signal Ic by a voltage-current conversion circuit (hereinafter referred to as VIC), and a current control oscillator (hereinafter referred to as ICO) is operated by the current signal Ic. Is.

  The LPF output voltage range can be output within the range of VSS (GND) to the power supply voltage VDD, but the effective range is necessary for the saturation operation of the MOSFETs constituting the current sources Iu and Id of the previous stage charge pump circuit (CP). It is reduced from the GND and VDD levels by an amount equivalent to the drain voltage. Further, when the filter voltage VC controlled by the VCO is used as the gate input of the MOSFET MN1, it is affected by the threshold voltage Vth of the MOSFET MN1. In particular, in the process for digital CMOS, the enhancement type is used for the purpose of reducing the current during non-operation, so that a non-conducting voltage region occurs, and the effective control voltage range of the VCO is (filter output voltage maximum value−threshold voltage). Decrease by threshold voltage.

  As shown in the characteristic diagram of FIG. 6, the control range narrows as the power supply voltage VDD decreases, and the threshold value cannot be reduced corresponding to the power supply decrease due to process miniaturization. Since the ratio of the occupying threshold increases as the miniaturization process increases, the decrease in the VIC voltage range of the VCO becomes greater than the power supply drop. This reduction in the control range reduces the subsequent oscillation frequency control range, increases the sensitivity to the VCO characteristics due to temperature and process deviation, and increases the variation. In order to secure a necessary oscillation frequency control range in the narrowed VIC voltage range, the VCO gain is necessarily set higher. However, a high VCO gain increases the influence of noise included in the VCO input, and degrades jitter performance. For this reason, it is conceivable to use a low threshold only for a MOSFET that receives a filter voltage as a method for mitigating the decrease in the control range. .

  An object of the present invention is to provide a semiconductor device including a PLL circuit which is suitable for a fine process and has a high performance. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the reference signal and the feedback signal are compared by the phase comparator. The charge pump circuit is controlled by the phase comparison output of the phase comparator, and the output current is supplied to the filter & voltage-current conversion circuit to control the oscillation circuit. The output signal of the oscillation circuit is divided by a frequency dividing circuit to form the feedback signal to constitute a PLL circuit. The filter & voltage-current conversion circuit includes an output MOSFET in which an output signal of a differential amplifier circuit in which a bias voltage is supplied to one input is supplied to a gate, a resistance element provided in a drain of the output MOSFET, A capacitor provided between the drain of the output MOSFET and the other input of the differential amplifier circuit. The output current of the charge pump circuit is supplied to the other input of the differential amplifier circuit.

  A voltage-current conversion output using the power supply voltage effectively can be obtained, and a VCO with good jitter characteristics can be realized.

  FIG. 1 is a circuit diagram showing one embodiment of a PLL circuit according to the present invention. The PLL circuit of this embodiment includes a frequency phase comparator PFD, a charge pump circuit CP, an active filter LPF + VIC with a voltage-current conversion function, a current control oscillator ICO, and a frequency divider 1 / N. The reference clock input signal Fref and the feedback clock signal FB are input to the frequency phase comparator PFD. The frequency phase comparator PFD outputs a down signal DWN / up signal UP having a pulse width corresponding to a phase difference (frequency difference) between rising edges of the reference clock input signal Fref and the feedback clock signal FB. When the reference clock input signal Fref advances with respect to the feedback clock signal FB, the up signal UP is set to a corresponding high level pulse width, and the down signal DWM remains at the low level. On the contrary, when the feedback signal FB is advanced, the down signal DWN is set to a corresponding high level pulse width, and the up signal UP remains at the low level. The three-state type charge pump circuit CP includes a current source Id, a switch SD, a current source Iu, and a switch SU. The switch SU / SD is switch-controlled by the down signal DWN / up signal UP, and is supplied to the current source Id. A corresponding pushing current or a sink current corresponding to the current source Iu is output.

  The capacitor CLP of the active filter circuit LPF at the next stage is charged / discharged by the charging current Id and the discharging current Iu formed by the charge pump circuit CP. In the active filter circuit LPF, a common source amplifier including a P-channel MOSFET MP2 and a resistor RP is arranged at the output of the differential amplifier AMP. This is an integrating circuit in which a capacitor CLP is connected between the non-inverting input terminal (+) of the differential amplifier AMP and the common source output VO. A reference voltage (bias voltage) VB is supplied to the inverting input terminal (−) of the differential amplifier AMP, and the charge / discharge current from the charge pump circuit CP is applied to the non-inverting input terminal (+) as described above. Supplied. The charge / discharge current (Id / Iu) from the charge pump circuit CP flows to the capacitor CLP, and the charge is accumulated. At this time, since the inverting input terminal (−) of the differential amplifier AMP of the capacitor CLP does not change with the reference voltage VB, only the voltage of the VO node that is the output of the common source amplifier changes. The VO node voltage indicates an integrated value of charge / discharge charges output by the charge pump circuit CP.

  The current that flows through the resistor RP of the common-source amplifier also flows through the P-channel MOSFET MP2 that is an amplifying element. When the current flowing through the MOSFET MP2 is Ic, Ic = VO / RP. The output voltage of the differential amplifier AMP that drives the gate of the MOSFET MP2 of the common-source amplifier similarly drives the gate of the P-channel MOSFET MP1 in the current-controlled oscillator ICO, and therefore the current that flows through the P-channel MOSFET MP1 of the current-controlled oscillator ICO. Is the same current Ic = VO / RP as in MOSFETMP2. The current Ic flowing through the MOSFET MP1 is supplied to a ring oscillator composed of inverter circuits IN1 to IN3, and an oscillation frequency Fosc corresponding to the current Ic is output via the output inverter circuit IN4. The MOSFETs MP2 and MP1 constitute a current mirror circuit, and have the same size when the same current flows.

  The oscillation output Fosc passed through the inverter circuit IN4 constitutes a closed loop (PLL) circuit as a feedback signal FB to the phase frequency comparator PFD through the frequency divider 1 / N. For example, when the feedback signal FB is delayed and the up signal UP of the phase frequency comparator PFD is at a high level, the switch SU of the charge pump circuit CP is turned on and the discharge current Iu passes through the P-channel MOSFET MP2 and becomes a capacitor. Since it flows to CLP, the voltage of the output VO rises. As the VO voltage rises, the current of the current controlled oscillator ICO also increases and the oscillation frequency rises. The increase in the oscillation frequency acts to eliminate the delay of the feedback signal FB. On the other hand, when the feedback signal FB is advanced and the down signal DWN of the phase frequency comparator PFD is high, the switch SD of the charge pump circuit CP is turned on and the charging current Id becomes the output voltage of the differential amplifier AMP. In order to decrease the current of the P-channel MOSFET MP2 and discharge the capacitor CLP by the resistor PR, the voltage of the output VO decreases. As the VO voltage decreases, the current of the current controlled oscillator ICO also decreases, and the oscillation frequency decreases. The decrease in the oscillation frequency acts to cancel the advance of the feedback signal FB.

  In addition to the phase difference integration function, the filter circuit LPF used in the PLL circuit requires a phase difference proportional component at the time of comparison for PLL stability. In the filter circuit LPF of FIG. 5, the capacitor CLP has an integration function, and the resistance RP voltage drop becomes a phase difference proportional component. It will be described below that the embodiment circuit shown in FIG. 1 also has a similar phase proportional component. As described above, the output VO indicates an integral output. During the period when the current flows from the output of the charge pump circuit CP to the capacitor CLP, the current flows through the P-channel MOSFET MP2 when the discharge current Iu, and flows through the resistor RP as described above when the current is the charge current Id. For this reason, the current flowing through the P-channel MOSFET MP2 only during this period increases or decreases by Id in addition to the current (VO / RP) determined by the filter output VO. The current flowing through the MOSFET MP2 is reflected in the MOSFET MP1 of the current controlled oscillator ICO. A current component that increases or decreases only during a pulse width period equal to this phase difference acts as a phase difference proportional component, and exhibits the same operation as the circuit of FIG.

  Switches S1 and S2 provided between both ends of the capacitor CLP and the ground potential of the circuit are provided for discharging the charge of the capacitor CLP and setting an initial value. The switches S1 and S2 are turned on during PLL standby, and are turned off during PLL operation. By turning on / off the switches S1 and S2, the PLL is activated from the standby state while the capacitor CLP is discharged, so that the initial filter output value (VO) after activation becomes the reference voltage VB, and Since the current for charging the reference voltage VB is supplied by the differential amplifier AMP having a large driving capability, the rise time is faster compared to the case of charging with a charge pump with a small current as in the circuit shown in FIG. Can be expected to shorten.

  The current control oscillator ICO is constituted by, for example, a ring oscillator constituted by CMOS inverter circuits IN1 to IN3. Between the P-channel MOSFETs of the CMOS inverter circuits IN1 to IN3 and the power supply voltage VDD, a P-channel MOSFET in which a current corresponding to the current Ic flows is provided. An N-channel MOSFET is provided between the ground potential VSS and a current corresponding to the current Ic. Alternatively, a inverting amplifier circuit is configured with a differential amplifier circuit, and a current source MOSFET provided on the common source side of the differential MOSFET is configured to allow a current corresponding to the current Ic to flow. In addition, the current control oscillator IOC may be any oscillation circuit as long as the frequency is variable by the current Ic from the P-channel MOSFET MP1.

  The filter output VO is the output of the common source amplifier of the drive MOSFET MP2 and the load resistor RP. If the drive capability of the P-channel MOSFET MP2 is designed to be sufficiently large, the output VO is at the GND level as shown in the characteristic diagram shown in FIG. Thus, an amplitude of approximately VDD level can be obtained. Accordingly, a current change corresponding to the amplitude flows to the MOSFET MP2 and is transferred to the current controlled oscillator ICO as a similar current change through the MOSFET MP1 sharing the gate. The current Ic is indicated by (VO / RP) and is determined only by the resistance, and the reduction of the control voltage range is eliminated in the output range of the charge pump circuit and the threshold value of the MOSFET as seen in the conventional circuit as shown in FIG. . When the power supply voltage VDD drops to near the threshold value Vth, the circuit of this embodiment is still not as good as the conventional circuit as shown in FIG. Since it has a control voltage range close to the value, it is suitable for low voltage operation.

  Since the control voltage range does not depend on the threshold voltage Vth, it can be used in multiple series generated by the threshold Vth setting in the same generation process in the CMOS fine digital process, and redesigned to each series It is possible to save design man-hours by eliminating That is, the problem that the MOSFET MN1 shown in FIG. 5 constituting the VIC must be formed by a special process in order to widen the control voltage range can be avoided.

  By providing the switches S1 and S2 as described above, when the PLL circuit is activated, the filter output starts to be pulled in from the reference voltage VB without preparing a starting charging circuit. Since the difference from the voltage VO can be reduced, the pull-in time can be shortened.

  FIG. 3 is a circuit diagram showing another embodiment of the PLL circuit according to the present invention. Non-Patent Documents 1 to 3 have already stated that the PLL circuit ensures the stability by switching the charge pump current values Iu and Id according to the multiplication number (N). In this way, in the case of self-bias that links the charge pump current with the oscillation current of the current controlled oscillator ICO, an activation circuit for charging up to an operation potential such as a filter capacitor when the PLL is activated is necessary. This embodiment circuit is a modification of the embodiment of FIG. 1 so that the charge pump current is linked to the current Ic of the current controlled oscillator ICO.

  A current mirror circuit composed of P-channel MOSFETs MP3, MP4 and MP5 and N-channel MOSFETs MN3, MN4 and MN5 is provided. A charge pump current that is β times the current Ic of the current controlled oscillator ICO is generated by the P-channel MOSFET MP3. The drain current of this MOSFET MP3 is passed through a diode-type N-channel MOSFET MMN3, and N-channel MOSFETs MN4 and MN5 are provided in the form of a current mirror with this MOSFET MN3. A drain current of the MOSFET MN4 is passed through a diode-type P-channel MOSFET MP4, and a PN channel MOSFET MP5 is provided in the form of a current mirror with this MOSFET MP4. The P-channel MOSFET MP5 is used as a current source of charge pump current Id, and the N-channel MOSFET MN5 is used as a current source of charge pump current Iu.

  The size ratio of the P-channel MOSFETs MP2 and MP3 is set to 1: β so that a current such as βIc flows through the MOSFET MP3. By making the size ratios of the N-channel MOSFETs MN3 to MN5 equal and the size ratios of the P-channel MOSFETs MP4 and MP5 equal, Id = Iu = βIc can be obtained. As described above, when the capacitor CLP is discharged by the standby switches S1 and S2 being turned on and then activated, both electrodes of the capacitor CLP rise to the reference voltage VB. Such a current for increasing the voltage across the capacitor CLP is not an indefinite charge pump current, but is supplied from the differential amplifier AMP-MOSFET MP2 and charged by parasitic capacitances at both electrodes of the capacitor CLP. No special circuit is required.

  When the output VO of the filter rises to the reference voltage VB, a current Ic corresponding thereto is formed and the current control oscillator ICO starts an oscillation operation. Since the value of the reference voltage VB can be set to a value close to the final value of the filter output VO within the operation input voltage range of the differential amplifier AMP, the charge pump currents Id and Iu are currents close to the final value immediately after activation. Pull-in operation can be performed by value. Generally, in order to widen the control range, the final value of the filter output VO is set near the midpoint potential of the power supply voltage VDD, so the reference voltage VB is also set near the midpoint voltage. The This means that the pull-in time can be shortened as compared with the case where the pull-in operation is started by starting from a low oscillation frequency and gradually increasing from a state where the charge pump current is small.

  In the embodiment of FIG. 3, P-channel MOSFETs MP6 and MP7 multiplied by α are provided for the P-channel MOSFET MP3. As a result, a current of αId flows through the MOSFET MP6, and a current of αIu flows through the MOSFET MP7. The MOSFETs MP6 and MP7 are provided with switches SD2 and SU2. The switch SD2 is switch-controlled by the down signal DWN of the phase frequency comparator PFD, and is normally turned off when the down signal DWN is set to the high level. The switch SU2 is switch-controlled by the up signal UP of the phase frequency comparator PFD, and is normally turned on when the up signal UP is set to a high level in the off state.

  When the output DWN of the frequency phase comparator PFD is formed, the switch SD2 is turned off and the current of the ring oscillator is decreased by βId to lower the frequency of the ring oscillator. Conversely, when the output UP of the frequency phase comparator PFD is formed, the switch SU2 is turned on and the current of the ring oscillator is increased by βIu to increase the frequency of the ring oscillator. In this way, the response of the PLL when the oscillation frequency fluctuates due to external noise or the like by directly controlling the frequency of the ring oscillator corresponding to the outputs DWN and UP of the frequency phase comparator PFD without interposing the LPF. Can be improved.

  FIG. 4 is a circuit diagram showing still another embodiment of the PLL circuit according to the present invention. As in this embodiment, not only the pure resistance R but also the MOSFET diode resistance by the diode-type MOSFET MN6 is used together as the load resistance of the output VO of the filter. The oscillation frequency of the current controlled oscillator ICO often has a saturation tendency characteristic in a region where the control current increases. Accordingly, the pure resistance R and the diode-type MOSFET MN6 can be used in combination, and the current-oscillation frequency can be corrected by the non-linearity of the current conversion characteristic to maintain the linear characteristic. Such a load resistance can also be applied to the embodiment circuit of FIG.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, in the embodiment, the switches S1 and S2 may be CMOS switches that short-circuit both electrodes of the capacitor CLP. The P-channel MOSFET and the N-channel MOSFET may be replaced with each other. For example, a differential amplifier may be configured with a P-channel MOSFET, the output signal thereof may be supplied to the gate of the N-channel MOSFET, and a resistor RP may be provided between the drain and the power supply voltage VDD. In this case, an N-channel MOSFET in the form of a current mirror may be provided in the N-channel MOSFET to obtain the operating current of the ring oscillator. The current may be amplified by a current mirror circuit to form an operating current of the ring oscillator. The present invention can be widely used for semiconductor devices having a PLL circuit.

1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. FIG. 2 is a characteristic diagram for explaining the operation of the PLL circuit of FIG. 1. It is a circuit diagram which shows another Example of the PLL circuit based on this invention. FIG. 6 is a circuit diagram showing still another embodiment of a PLL circuit according to the present invention. It is a circuit diagram of a PLL circuit studied prior to the present invention. FIG. 6 is a characteristic diagram for explaining the operation of the PLL circuit of FIG. 5.

Explanation of symbols

  MP1 to MP7 P channel MOSFET, MN1 to MN6 N channel MOSFET, PFD phase detector, CP charge pump circuit, LPF & VIC active filter with voltage-current conversion, ICO current controlled oscillator, 1 / N Frequency divider circuit, CLP ... capacitor, S1, S2, SD, SU ... switch, IN1-IN4 ... inverter circuit.

Claims (8)

A phase comparator that receives the reference signal and the feedback signal;
A charge pump circuit for receiving a phase comparison output of the phase comparator;
A filter and voltage-current conversion circuit receiving the output current of the charge pump circuit;
An oscillation circuit whose oscillation frequency is controlled by the output current of the voltage-current conversion circuit;
A PLL circuit having a frequency dividing circuit for receiving the output signal of the oscillation circuit and forming the feedback signal;
The filter & voltage-current converter circuit
A differential amplifier circuit in which a bias voltage is supplied to one input;
An output MOSFET in which the output signal of the differential amplifier circuit is supplied to the gate;
A resistance element provided at the drain of the output MOSFET;
A capacitor provided between the drain of the output MOSFET and the other input of the differential amplifier circuit;
The output current of the charge pump circuit is supplied to the other input of the differential amplifier circuit,
The semiconductor device is a ring oscillator in which the oscillation frequency is controlled by the output MOSFET and a first MOSFET in a current mirror form. In claim 1,
A semiconductor device having a switch for discharging the capacitor before the PLL circuit starts operation. In claim 2,
The switch is a semiconductor device comprising first and second switches provided between both electrodes of the capacitor and the ground potential of the circuit. In claim 2,
A second MOSFET in the form of a current mirror with the output MOSFET;
A semiconductor device further comprising: a current mirror circuit that receives a current flowing through the second MOSFET and generates a charge pump current of the charge pump circuit. In claim 4,
A first MOSFET and third and fourth MOSFETs in the form of a current mirror;
A third switch and a fourth switch for supplying drain currents of the third and fourth MOSFETs to the ring oscillator;
The third switch is controlled by a down output of a phase comparison output of the phase comparator to be turned from an on state to an off state and reduce a current supplied to the ring oscillator,
The fourth switch is a semiconductor device that is controlled by an up output of a phase comparison output of the phase comparator and is turned from an off state to an on state to increase a current supplied to the ring oscillator. In claim 4,
The current mirror circuit is
A fifth MOSFET in the form of a diode in which the drain current of the second MOSFET flows;
Sixth and seventh MOSFETs in the form of current mirrors with the fifth MOSFET;
An eighth MOSFET in the form of a diode in which the drain current of the sixth MOSFET flows;
The eighth MOSFET and the ninth MOSFET in the form of a current mirror;
The seventh MOSFET forms one charge pump current of the charge pump circuit,
The ninth MOSFET is a semiconductor device for forming the other charge pump current of the charge pump circuit. In claim 3,
The semiconductor device in which the bias voltage is set near the midpoint voltage of the power supply voltage. In claim 3,
The resistance element is a semiconductor device including a diode-type MOSFET.

Images